Abstract: Methods and systems for diversity processing including using dedicated pilot method for closed loop may include combining a plurality of received WCDMA/HSDPA multipath signals for each diversity transmit antenna to at least one processed diversity signal. The received WCDMA/HSDPA multipath signals may originate from diversity transmit antennas at a base station that may be transmitting information via a closed loop or open loop diversity transmission mode. The closed loop diversity transmission mode may be closed loop 1 or closed loop 2. Estimations may be made of the closed loop transmit weights used by the base station for transmission of the symbols. Closed loop symbols transmitted by the diversity transmit antennas may then be estimated based on received diversity signals and at least one dedicated pilot channel. Open loop symbols may be estimated using information from at least one common pilot channel.

Abstract: In a wireless communication system, a method and system for extending Advanced Encryption Standard (AES) operations for enhanced security are provided. In an AES encryption operation, an initial state may be modified by XORing with an initial modifier before a first processing round and a final state may be modified by XORing with a final modifier after a final processing round. The output of a MixColumns function performed during AES decryption operation rounds may be modified by XORing with a corresponding round modifier. In an AES decryption operation, an initial state may be modified by XORing with a decoded final modifier before a first processing round and a final state may be modified by XORing with a decoded initial modifier after a final processing round. The input of an InvMixColumns function performed during AES decryption operation rounds may be modified by XORing with a corresponding decoded round modifier.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: A method and system for decoding video, voice, and/or speech data using redundancy and physical constraints are presented. Video, voice, and/or speech bit sequences may be decoded in a multilayer process based on a decoding algorithm and at least one physical constraint. For voice applications, the decoding algorithm may be based on the Viterbi algorithm. At least one estimated bit sequence may be selected by performing searches that start from trellis junctions determined during by the decoding algorithm. The estimated bit sequences may be selected based on corresponding redundancy verification parameters. At least one physical constraint test may be performed on the selected estimated bit sequences to select a decoded output bit sequence.

Abstract: An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.

Abstract: A method and apparatus for providing assistance data for satellite positioning system receivers utilizing a secure user plane location (SUPL) service. In one embodiment, the assistance data is supplied by a global secure user plane location center that contains global assistance data.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

Abstract: Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

Abstract: Embodiments of this invention comprise a modular, scalable architecture for building a variety of Layer 2/3/4+ Ethernet products and devices. Such devices comprise of a set modules. The invention provides a set of rules to handle such modules. The rules are controlled by the architectural component named card manager. The card manager uses a protocol to discover the modules that are entering or leaving the system/device. The protocol's data provides a unique way of identifying the modules that belong to the system.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information received at a digital video input. An artificial time stamp module is used to generated the pseudo MPEG information from associating an artificial time stamp with the digital video information. This pseudo MPEG information is received, for example, at an MPEG signal processor in a set-top box. The MPEG signal processor decodes the pseudo MPEG information and outputs the decoded MPEG information under control of the artificial time stamps.

Abstract: A primary multi-layer protocol stack that allows a secondary multi-layer protocol stack to communicatively couple into one or more of its layers. End point device circuitry implements both the primary and secondary protocol stacks. A communication application running on the end point device initiates interaction, e.g., a session, via a primary radio and primary intermediate protocol stack layers. Based on a change in communication characteristics, for example, an operation is invoked to bridge between one of the intermediate protocol stack layers of the primary stack to one from the secondary stack. Such bridging establishes a secondary pathway via the secondary radio. The primary and secondary radios may support the same or differing protocols. To avoid having to fully reestablish a session, at least one session parameter is carried forward through the bridge. The bridge may have multiple entry points in and out of both protocol stacks and operate as two half-duplex bridges.

Abstract: A differential amplifier with surge protection is described. The differential amplifier includes a first output driver device, a second output driver device, a first replica device, a second replica device, a current comparator, and a clamp circuit. The first replica device is configured to be a replica of the first output driver device. The second replica device is configured to be a replica of the second output driver device. The current comparator is configured to generate a threshold current, and to compare the threshold current to a first current through the first replica device and a second current through the second replica device. The clamp circuit is configured to limit a third current through the first output driver device and a fourth current through the second output driver device if the current comparator determines that the threshold current is greater than the first current or the second current.

Abstract: A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A radio frequency (RF) tuner includes a programmable tracking filter bank receiving an RF input and outputting a filtered RF signal. A mixer stage receives the filtered RF signal and outputs a first quadrature component of the filtered RF signal and a second quadrature component of the filtered RF signal. Two variable gain amplifiers receive the first and second quadrature components and output amplitude-controlled I and Q components of the filtered RF signal. In one embodiment, the programmable tracking filter bank includes a plurality of tank circuits each connected to the RF input through an impedance. Each tank circuit include an inductor and a capacitor connected in parallel thereby forming an LC network, and a plurality of switched capacitors in parallel with the LC network and switched in and out of the tank circuit by programmable switches. In another embodiment, the programmable tracking filter bank includes a plurality of peaked low-pass circuits each connected to the RF input through an impedance.

Abstract: A Space Time Transmit Diversity (STTD) Decoder includes a physical channel despreader, a delay buffer, an upper processing branch, a lower processing branch and a combiner. The upper processing branch is operable to apply a conjugate of a first channel estimate to the delay buffer symbol output and produce non STTD encoded symbols. The lower processing branch is operable to read delayed delay buffer symbol outputs and apply a conjugate of a second channel estimate when active in the STTD mode. The lower processing branch then may apply an STTD decoder scheme to the delay buffer symbol output to produce non STTD encoded symbols. The combiner then combines the non STTD encoded symbols of the upper processing branch and non STTD encoded symbols of the lower processing branch to produce a single set of non STTD encoded symbols.

Abstract: A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and a power management unit. The wireless interface unit wirelessly interfaces with the wirelessly enabled host using a communication interface protocol. The power management unit couples to the wireless interface unit, the processing unit, and the input/output unit. The wireless interface unit supports paging operations in which the wireless interface device is able to receive a page during a wirelessly enabled host in a page scanning period that corresponds to a duration of the page hopping sequence of the host.