Abstract: A system for selectively blocking and unblocking the sending of outgoing caller ID information from a communication device comprises a communication device, a processor coupled to the communication device and a storage medium coupled to the processor containing a directory of information entries. The information entries include both telephone numbers and associated security levels. When a call is placed to a number using the communication device, the processor seeks the number in the directory of the storage medium. If an entry is found for the number by the processor, caller ID information is prevented from being sent to the number unless a security level associated with the number is at or above a predefined cut-off level.

Abstract: A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver.

Abstract: A wireless access point selects its own transmission power for different types of the transmissions.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: A receiver front end includes a plurality of in-phase and quadrature phase receive processing blocks operable at first and second frequency bands and further includes a plurality of filtering and amplification blocks disposed within a corresponding ingoing signal path, a plurality of received signal strength indicator (RSSI) blocks coupled to receive an ingoing analog signal from a corresponding plurality of nodes disposed throughout the ingoing signal path, each of the plurality of RSSI blocks producing a signal strength indication, and wherein a baseband processor is operable to receive a selected signal strength indication and to produce at least one gain setting to at least one amplification block within the in-phase or quadrature phase receive processing blocks. In operation, the baseband processor receives a signal strength indication from each RSSI block to determine a total amount of gain and appropriate gain distribution within the receive signal path.

Abstract: An integrated circuit includes a on-chip pressure sensing circuit that generates a pressure signal based on a pressure of the integrated circuit. A processing module, generates a control signal based on the pressure signal. An RF transceiver generates an outbound RF signal from outbound data and to generate inbound data from an inbound RF signal, based on the control signal.

Abstract: A radio frequency (RF) front-end includes a plurality of power amplifier modules and a plurality of impedance matching circuits. Each of the plurality of impedance matching circuits includes an input connection and an output connection, wherein outputs of the plurality of power amplifier modules are coupled to corresponding input connections of the plurality of impedance matching circuits to provide a desired loading of the plurality of power amplifier modules and wherein the output connections of the plurality of impedance matching circuits are coupled together to add power of the plurality of power amplifiers.

Abstract: An system comprising an ingress device configured to receive and process data, wherein the ingress device comprises a plurality of processing stages configured to process the data, wherein a configurable subset of the stages comprises a selectable tap point, and wherein the ingress device is further configured to, upon reaching a selected tap point, suspend processing and send at least a portion of the data to another device; an offload engine device configured to receive data from the ingress device, after the selected tap point has been reached, and to provide additional processing of the data, which the ingress device is not configured to provide; an egress device configured to transmit the data that has been additionally processed by the offload engine device.

Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data transmission and the like. The data recorder has the capacity to selectively choose the most relevant time frames of a conversation for recording, while discarding time frames that only occupy additional space in memory without holding any conversational data. The invention executes a series of logic steps on each signal including a voice activity detector step, frame comparison step, and sequential recording step. A mobile set having a modified architecture for performing the methods of the present invention is also disclosed.

Abstract: A midspan power sourcing equipment (PSE) for operation with power over Ethernet (PoE). The midspan PSE provides powering over wire pairs that are also used for data communication. To ensure compatibility with legacy Ethernet devices, the ports used for transmission of data are designed to present an increased level of inductance.

Abstract: A system for processing radio frequency (RF) signals includes a searcher and a plurality of Cluster Path Processor (CPPs). The searcher detects a maximum signal energy level and position of at least one of a plurality of individual distinct path signals in a signal cluster of a first information signal, wherein at least a portion of the plurality of individual distinct path signals is received within a duration of a corresponding delay spread. The sampling position is used as a starting sampling location by the plurality of CPPs, including a first information signal CPP and a second information signal CPP. Fine sampling positions of the plurality of CPPs are based upon channel energy estimates for the plurality of individual distinct path signals. CPP outputs are employed to produce channel estimates, which are themselves used in subsequent equalization operations. Sampling positions may change over time in order to satisfy alignment criteria.

Abstract: Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a System-On-a-Chip(SOC) unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).

Abstract: An apparatus comprising a plurality of fixed logic circuits, wherein each of the fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, and wherein the combinational logic operations are substantially fixed; and a programmable logic core configured to functionally replace a selected subset of the plurality of fixed logic circuits, receive the input signals of the selected subset of the plurality of fixed logic circuits, perform logic operations on the input signals, and produce at least one output signal as the output signal of the selected subset of the plurality of fixed logic circuits, and wherein the logic operations are dynamically changeable.

Abstract: Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.

Abstract: Herein described is a system and method that tracks the face of a person engaged in a videophone conversation. In addition to performing facial tracking, the invention provides stabilization of facial images that are transmitted during the videophone conversation. The face is tracked by employing one or more algorithms that correlate videophone captured facial images against a stored facial image. The face may be better identified by way of employing one or more voice recognition algorithms. The one or more voice recognition algorithms may correlate utterances of the person engaged in a conversation to one or more stored utterances. The identified utterances are subsequently mapped to a stored facial image. In a representative embodiment, the system used for performing facial tracking and image stabilization comprises an image sensor, a lens, an actuator, and a controller/processor.

Abstract: A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data symbols such that a specified pattern of K data symbols and N?K null symbols is formed in every period of N symbols in the modulated sequence, N and K being positive integers and K being smaller than N.

Abstract: Aspects of a method and system for extending dynamic range of an RF signal are provided. In this regard, a signal representative of an amplitude of a pair of baseband signals may be generated. The amplitude of the generated signal may be expanded, and the amplitude of the baseband signals may be compressed. In this regard, the compression and the expansion may be inverse functions of each other. Additionally, the compressed baseband signals may be combined to generate an intermediate signal which may be amplitude modulated by the expanded signal. The amplitude modulation may result from controlling a gain, a voltage source, and/or a current source of a power amplifier. The intermediate signal may be generated by up-converting the baseband signals and subsequently combining the up-converted signals.

Abstract: Methods and systems for level detector calibration are disclosed and may comprise calibrating a level detector integrated on-chip to eliminate an associated zero input offset voltage utilizing a replica bias circuit with no input ac voltage at the level detector or the replica bias circuit. The offset voltages of the level detector and the replica bias circuit may be combined to eliminate the associated zero input offset voltage of the level detector. The output signal may be generated by a difference of output signals from the level detector and the replica bias circuit. The level detector and the replica bias circuit may be biased utilizing a similar bias voltage. A plurality of known input voltages may be utilized to generate a corresponding plurality of output voltages of the level detector, generating a corrected transfer function that may be used to accurately set a transmitter power level.

Abstract: Providing link quality intelligence from physical layer to higher protocol layers. The PHY (physical layer) of devices operating within wireless communication systems assess 1 or more operational parameters corresponding to a PHY link that communicatively couples 2 or more devices. These PHYs provide this assessed intelligence to the devices' higher protocol layers so that these higher protocol layers have greater visibility of the operational parameters of the PHY link. These higher protocol layers may use this assessed intelligence to make decisions about how future communication are governed across the PHY links. For example, based on a change of the operational parameter(s), the higher protocol layers may modify the operational parameter(s) for future communications. The higher protocol layers may direct the PHY to assess a particular set of operational parameters, and the higher protocol layers may assess different operational parameters at different times.