Abstract: An improved dither generation circuit and method for digital audio circuits uses a high-pass filter to reduce the energy contained in the audio band of the dither signal. The resulting dither signal is applied to the circuit in its main feedback loop and is effective to prevent idle tones. Because of its spectrally shaped characteristic this dither signal introduces less noise into the audio band of interest and thereby improves the overall signal-to-noise ratio of the audio circuit. In an embodiment, the dither signal is generated using pseudo-random numbers that are then interpreted as 2's complement numbers.

Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Abstract: Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate) frequency controlled by a numerically controlled oscillator. To regulate the frequency of the signals from the numerically controlled oscillator, the phases of the clock signals at the variable frequency are compared in a phase detector with the phases of the signals from the numerically controlled oscillator to generate an error signal. The error signals and the signals at a fixed sampling frequency higher than the intermediate frequency regulate the frequency of the signals from the numerically controlled oscillator and thus the frequency of the digital data signals from the FIFO. The digital data signals from the FIFO are converted to a pair of signals at the second frequency.

Abstract: A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked loop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked loop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A system and method for reducing noise in a substrate of a chip is provided. The system may include a substrate (70) doped with a first dopant. A first well (80) may be disposed on the substrate and doped with a second dopant. A second well (120) may be disposed within the first well (80) and doped with the second kind of dopant. A first transistor (100) may include one or more first transistor components disposed in the second well (120). The first transistor (100) may be adapted to employ a first type of channel having a quiet voltage source (140) connected to a body thereof. A third well (110) may be disposed within the first well (80) and doped with the first kind of dopant. A second transistor (90) may include one or more second transistor components that may be disposed in the third well (110). The second transistor (90) may be adapted to employ a second type of channel. The first well (80) may shield the substrate (70) from noise in the second well (120) and third well (110).

Abstract: A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: Home phone line network devices, conforming to different versions of the standards, are interconnected and interoperable on a UTP transmission medium. Higher order devices support an overlaid dual logical network structure which allows two pairs of higher order devices to communicate simultaneously using two separate frequency bands. A higher order node contains a high speed PHY, a low speed PHY, and either a high and low order MAC or an enhanced MAC capable of supporting dual frequency band transmission, thereby enhancing total system throughput to the sum of the throughputs of each logical network.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.

Abstract: A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each controlled by an input signal, a first voltage input and a second voltage input, and a signal output. The first voltage controlled voltage source is connected to the first voltage input. The first voltage controlled voltage source has a low impedance. The second voltage controlled voltage source is connected to the second voltage input. The second voltage controlled voltage source also has a low impedance. The switching circuit outputs an output signal having an output voltage and current controlled by the first and second voltage controlled voltage sources. The output signal is based upon the input signal.

Abstract: A translational-loop transmitter includes a local oscillator (LO) generator for generating first and second LO signals, a modulator for generating a modulated reference signal using the second LO signal, and an offset phase-locked-loop (PLL) for phase-locking an output signal to the reference signal, and for tuning the output signal in accordance with the first LO signal. The PLL includes an offset mixer in a feedback path of the PLL, and operates in accordance with a frequency plan that minimizes the effects of on- and off-channel spurs at the output of the offset mixer.

Abstract: A system method, and apparatus for decoding a bitstream comprising variable length coded symbols are presented herein. The bitstream is parsed and the symbols that are decoded are extracted from the bitstream. The symbols that are not decoded in the parse are stored in a register. When the register is full, the contents therein are stored in the next available data word in the memory. In the foregoing manner, the bitstream without the decoded symbols is stored continuously in memory, even where the width of the memory is substantially wider than the variable length symbols.

Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: A sigma-delta modulator includes a summing junction that receives an input signal. A plurality of integrators are arranged in series, the integrators output an integrated signal value to a multi-input quantizer. The multi-input quantizer has a plurality of comparators each with switched capacitor inputs. The multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC that drives the summing junction.

Abstract: The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.