Abstract: A system includes a support device and an elongated spiral antenna coupled to the support device. The elongated spiral antenna has a contracted portion and an expanded portion. The expanded portion provides beam steering and directivity. The system also includes a feed line coupled to the elongated spiral antenna. A method for forming the elongated spiral antenna uses a predetermined formula to form arms of the elongated spiral antenna. The arms can be formed by printing the arms on a printed circuit board.

Abstract: A switched capacitor circuit having an integrator, a switch, a capacitor, a field effect transistor, and a network. The switch is connected to the integrator. The capacitor is connected to the switch. The field effect transistor is connected to the capacitor. The network is connected to a gate terminal of the field effect transistor. The network is configured to control a resistance of the field effect transistor in response to variations in an input signal voltage received at the field effect transistor.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Abstract: A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.

Abstract: Disclosed herein is a method for processing information in a primary communication channel. The method may include encoding at least one portion of at least one word of at least one packet in a communication datastream. The method may also include reversing a running disparity of an encoded portion of the at least one word. In an embodiment according to the present invention, the method may provide a secondary communication channel being overlaid onto a primary communication channel by applying an encoding method to effectively expand the utilizable information capacity of the primary communication channel.

Abstract: A demodulator (10) converts television signals to video baseband signals and audio baseband signals including stereo signals representing a right channel signal value and a left channel signal value. A DSP (60) recursively finds a preferred coefficient value for a scaling that reduces stereo separation due to amplitude variation of the right and left channel signal values. The preferred coefficient value is thereafter used for scaling the right and left channel signal values.

Abstract: An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is coupled to a first node. The first transistor drives a first state on the first node responsive to an assertion of the first dynamic data signal. The second transistor is coupled to the first node and has a second control terminal. The second transistor is drives a second state on the first node responsive to a signal on the second control terminal. The circuit is coupled to generate the signal on the second control terminal and is coupled to receive a second dynamic data signal. The second dynamic data signal is a complement of the first dynamic data signal, wherein the circuit is activates the second transistor responsive to an assertion of the second dynamic data signal.

Abstract: An apparatus for providing bias voltages for input/output (I/O) connections on low voltage integrated circuits. In one embodiment, the invention comprises an I/O pad, a pull-down transistor device that has a protective transistor coupled to said I/O pad, and a pull-up transistor device that has a second protective transistor, coupled to said I/O pad. A first switch coupled to the first protective transistor is responsive to a first supply voltage, a second supply voltage, and a reference voltage. Likewise, a second switch coupled to the second protective transistor is responsive to the first supply voltage and the reference voltage. A first self-bias circuit is also coupled to the first switch, wherein said the self-bias circuit uses a voltage at said I/O pad to bias the first protective transistor when both of the first and second supply voltages are powered off.

Abstract: A network switch having an internet port interface controller, includes a high performance interface for communicating with other switches and components through the transfer of data packets contained in memory. The high performance interface includes a data connection bus, where data is transferred on both a rising edge and a falling edge of a clock signal, and the data connection bus has output drivers and a multiplexing circuit connected to the output drivers. The multiplexing circuit is constructed through two levels of glitchless multiplexors, to serialize said data transmitted over said high performance interface. Because two levels of glitchless multiplexors are employed, function hazards that occur in the glitchless multiplexors when more than one input thereto change simultaneously can be masked, and do not create noise that can be propagated to an output driver.

Abstract: Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.

Abstract: A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. In an embodiment, rising and/or falling edge slopes are monitored. For example, a dV/dt may be monitored. The dV/dt can be monitored by coupling a capacitance to the output signal, generating a current with the capacitance, and generating a voltage from the current. The voltage is generally proportional to the dV/dt. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: An BTSC encoder with an improved digital filter structure substantially implemented on a single CMOS integrated circuit is described. By cascading first and second order allpass filter structures to form a higher order digital filter, such as a Cauer low pass filter, limit cycle oscillations are reduced or eliminated, word-length growth from one stage to the next is contained, and a more efficient overall filter structure and performance is obtained.

Abstract: A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By incorporating a BTSC encoder within an all digital RF modulator, an improved set top box is provided, obviating the need for an additional BTSC encoder and modulator board and/or discrete analog components. A fully integrated solution that performs BTSC encoding within the RF modulator may be used with legacy television systems and also with other audio/visual equipment connected to the set top box.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of the feedback control signal in regions of operation where the calculation for the control signal is dominated by noise, an integrated circuit selectively adjusts the control signal for the spectral or wideband feedback loop, as required, so that the performance of a very low noise digital BTSC encoder complies with the requirements of the BTSC standard.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.