Abstract: A method of flow control management of data packets in a switch. The method has the steps of determining each time data is being written to memory in order to calculate a memory used amount; determining each time data is being freed from memory in order to calculate a memory freed amount; and calculating how much total memory is being used using the memory freed amount and the memory used amount. A comparison is made comparing the total memory being used to a first predetermined threshold. When the first predetermined threshold is reached a first threshold command is issued indicating that the first predetermined threshold has been reached.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: An apparatus for converting a signal from a first analog format to a second analog format. The apparatus has an input port, a first converter, filters, first mixers, second converters, and an output port. The input port is configured to receive the signal. The signal has the first analog format. In an embodiment, the first analog format complies with the SCTE 40 2003 technical standard. In an embodiment, the second analog format is a conventional analog format. The first converter is coupled to the port and is configured to convert the signal to a first digital format. The filters are coupled to the first converter and configured to isolate a first channel of the signal from a second channel of the signal. The first mixers are coupled to the filters and configured to expand the first channel and the second channel to a second digital format. The second converters are coupled to the first mixers and configured to convert the first channel and the second channel to the second analog format.

Abstract: An apparatus for tuning a frequency conversion device. The apparatus has a channel identifier, a channel cross-referencer, and a frequency conversion device tuner. The channel identifier is configured to identify a first channel to which a receiver is tuned. The channel cross-referencer is coupled to the channel identifier and is configured to cross-reference the first channel with a second channel. The frequency conversion device tuner is coupled to the channel cross-referencer and is configured to tune the frequency conversion device to the second channel. An apparatus for processing a signal. The apparatus has an input port, a signal format identifier, a switch, a converter, an output port, and a bypass signal path. The input port is configured to receive the signal. The signal format identifier is coupled to the input port and configured to identify the signal as having a first format or a second format. The switch is coupled to the signal format identifier.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: A system for reducing the cost of network managment by using a proxy agent and subchannel communications so fewer SNMP licenses and fewer protocol stacks are needed. Subchannel communication is achieved in a plurality of different embodiments. Embodiments having single subchannel transceivers, multiple transceivers, single multiplexer and multiple multiplexers are disclosed. An NMS process using routing table CRC to automatically detect when the NMS topology information is incorrect and automated topology discovery is disclosed. A process for automated discovery of redundant cables during automated topology discovery is disclosed.

Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a first clock frequency, alternating between a first level and a second level, wherein the first data rate is twice the first clock frequency. A first signal is generated by passing the data signal when the clock signal is at the first level, and storing the data signal when the clock signal is at the second level. A second signal is generated by passing the data signal when the clock signal is at the second level, and storing the data signal when the clock signal is at the first level. A third signal is generated by passing the first signal when the clock signal is at the second level, and storing the first signal when the clock signal is at the first level.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Abstract: A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a continuing interconnection coupled to the first and second spiral conductive patterns; an interface coupled to the first and second spiral conductive patterns; and a conductive shield pattern disposed on a third surface that is adjacent to the second surface. The interface includes a first terminal disposed on the first surface that is coupled to the first spiral conductive pattern. The interface also includes a second terminal that is disposed on the first surface and coupled to said second spiral conductive pattern.

Abstract: A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

Abstract: Video encoding device including a video input processor, for receiving said video signal, a global controller, for controlling the global operation of the video encoding device, a motion estimation processor, a digital signal processor and a bit-stream processor, wherein the global controller stores encodes commands received from a host interface thereby programming the video input processor, the motion estimation processor, the digital signal processor and the bit-stream processor, the video input processor receives and stores the video signal in an external memory unit, the motion estimation processor retrieves the video signal from the memory unit, generates motion analysis of the video signal, stores the motion analysis in the memory unit and provides the motion analysis to the digital signal processor, the digital signal processor processes the video signal according to the motion analysis, thereby producing an encoding commands sequence and encoded data, the bit-stream processor produces an encoded vide

Abstract: The present invention relates to a hybrid circuit for bidirectional communication over a communication line, the hybrid circuit directing a transmit signal inputted at an input line to the communication line and directing a receive signal received on the communication line to an output line different to the input line, the input line and the output line being coupled with a primary side of a transformer, the secondary side of the transformer being coupled with the communication line. Optionally, the hybrid circuit can be used within a communication system for a digital subscriber line. The primary side of the transformer comprises two coils with a first terminal and a second terminal respectively, the coils being connected in series via a middle impedance arranged between the first terminals of the coils.

Abstract: Aspects of the method for reducing noise in the substrate may comprise doping a substrate with a first dopant and doping a first well disposed on the substrate with a second dopant. The first well may be a deep well. A second well disposed within the first well may be doped with a second dopant. A first transistor having a first transistor channel type and one or more transistor components may be disposed within the second well. A quiet voltage source may be coupled to a body of the first transistor. A third well disposed within the first well may be doped with the first dopant. A second transistor having a second transistor type and one or more transistor components may be disposed within the third well. In this arrangement, disposing the first well between the substrate and the second well may reduce noise in the substrate.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or pre-determined, rate of voltage change.

Abstract: A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.

Abstract: A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

Abstract: Method for transmitting messages in a communications system, wherein the message is segmented into a plurality of message segments, the message segments being of variable length, the plurality of message segments comprising at least one leading message segment and a trailing message segment, and a message segment indication is applied to the at least one leading message segment.

Abstract: A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module (135). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier (170).