Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A method performs automated at-speed testing of devices. The method includes the steps of generating multiplexer control signals, forming various signal paths between a set of multiplexers and the devices based on the multiplexer control signals, and routing test signals having multiple gigabit per second (MGBPS) baud rates through the signal paths.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory capacity. Data packets to be transmitted upstream are stored at the cable modem. The data packets each have a given transmission data byte length value. Burst profiles are received successively at the cable modem. Each time a new bust profile is received, a set of physical data length values corresponding to respective transmission data byte length values is calculated from the parameters of the received burst profile. The calculated set of physical data length values is stored in memory so the individual values can be retrieved from the transmission data byte length values again and again, rather than being re-calculated each time a conversion is made from transmission data byte length values to physical data length values. The same set of physical data length values is used until a new burst profile is received by the cable modem.

Abstract: A method for flexibly configuring default values of a network device through an EEPROM interface is disclosed. A header is received from an EEPROM through the EEPROM interface and it is determined from the header whether any default value of the network device should be updated, and if any, how many should be updated. At least one configuration instruction is fetched from the EEPROM when it is determined that the network device should be updated. The at least one configuration instruction is interpreted and a register default value of the default values corresponding to the interpreted at least one configuration instruction is changed.

Abstract: A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.

Abstract: A testing system performs simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates coupled to a DIB and device connectors on the DIB. The testing system includes a rider board including rider board connectors coupled to corresponding ones of the device connectors, an individual set of multiplexers coupled to each one of said rider board connectors, a controller coupled to each of said set of multiplexers, and an internal testing system including a tester and testing system multiplexers, said tester being coupled to each of said set of multiplexers via said testing system multiplexers.

Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.

Abstract: A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

Abstract: In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.

Abstract: The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states 2 and transitions 4 determined by weights W1, W2 . . . W10 is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.

Abstract: A system for implementing personal video recording, in which integrated drive electronics are incorporated in set-top box logic, instead of with a hard disk drive. This allows the set-top box logic to communicate directly to the hard disk, so that no intervening bus is necessary.

Abstract: A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Abstract: A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.