Patents Assigned to Broadcom
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Publication number: 20030225561Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.Type: ApplicationFiled: March 12, 2003Publication date: December 4, 2003Applicant: Broadcom CorporationInventors: Luis Garcia, Russell E. Vreeland, Christopher B. Novak, Gabriel G. Marasigan, Christopher A. Roussel
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Patent number: 6657491Abstract: A system is provided for activating gain stages in an amplification module. The system includes an amplification module including a first group of amplifiers. Inverting output ports of each of the first group of amplifiers are coupled to a module inverting output terminal, and non-inverting output ports are coupled to a module non-inverting output terminal. A divider network is provided and is coupled to the input ports of the first group of amplifiers. A second group of amplifiers is also provided. Each amplifier of the second group corresponds to one of the amplifiers in the first group, has an inverting input port coupled to the second module inverting input terminal and to output ports of the divider network, and a non-inverting input port coupled to the second non-inverting input terminal.Type: GrantFiled: August 8, 2002Date of Patent: December 2, 2003Assignee: Broadcom CorporationInventors: Adel Fanous, Leonard Dauphinee, Lawrence M. Burns, Donald McMullin
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Patent number: 6657462Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.Type: GrantFiled: January 22, 2003Date of Patent: December 2, 2003Assignee: Broadcom CorporationInventor: Daniel W. Dobberpuhl
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Patent number: 6657503Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.Type: GrantFiled: April 25, 2002Date of Patent: December 2, 2003Assignee: Broadcom CorporationInventor: Bin Liu
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Patent number: 6658016Abstract: A packet switching fabric includes means forming a data ring, means forming a control ring, and means forming a plurality of data communication network links each having at least one network node coupled thereto. The fabric further includes a plurality of output queuing controlled switching devices coupled together by the data ring means and the control ring means so that the network links can be selectively communicatively coupled. Each of the output queuing controlled switching devices includes control ring processing means operative to develop, transmit and receive control messages to and from adjacent ones of the devices via the control ring means.Type: GrantFiled: February 29, 2000Date of Patent: December 2, 2003Assignee: Broadcom CorporationInventors: William Dai, Jason Chao, Yao-Ching Liu
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Publication number: 20030218560Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.Type: ApplicationFiled: June 13, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Jan Mulder, Christopher Michael Ward
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Publication number: 20030220956Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.Type: ApplicationFiled: April 23, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Keshab K. Parhi, Jin-Gyun Chung, Sang-Min Kim
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Publication number: 20030218556Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: February 6, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Publication number: 20030219009Abstract: A system for tunneling wideband telephony, comprises a communication device configured to produce a compressed wideband audio signal. The compressed wideband audio signal has (i) an audio frequency passband greater than that of an 8 kHz sampled audio signal, and (ii) a compressed data rate that is less than or equal to 64 kbps. The system also includes an apparatus, such as a voice gateway, coupled to the communication device and a data link, including a transcoder bypass configured to convert, without transcoding, the compressed wideband audio signal into a data stream including wideband compressed audio data for transmission over the data link.Type: ApplicationFiled: November 21, 2002Publication date: November 27, 2003Applicant: Broadcom CorporationInventor: Kenneth J. Unger
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Patent number: 6654378Abstract: A communication system including a battery powered mobile service station is used to provide transactional support within a premises. The mobile service station includes a plurality of network devices that operate on a second wireless network, where at least one of the plurality of network devices participates on a first wireless network. In one embodiment, a network device participates as a slave device on the first wireless network and participates as a master device in the second wireless network. In another embodiment, a mobile service station includes a mobile network device that simultaneously operates over a wireless premises network and a wireless peripheral sub-network having a relatively shorter range than the wireless premises network. One or more peripheral devices communicate with the mobile network device in the peripheral sub-network. The mobile service station includes a battery power supply and may further include a peripheral device coupled to the battery.Type: GrantFiled: July 7, 1995Date of Patent: November 25, 2003Assignee: Broadcom Corp.Inventors: Ronald L. Mahany, Steven E. Koenck, Alan G. Bunte, Robert C. Meier, Phillip Miller, Roger L. Wolf, George E. Hanson
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Patent number: 6653876Abstract: A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.Type: GrantFiled: April 23, 2002Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Sami Issa, Morteza (Cyrus) Afghahi
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Patent number: 6653966Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: February 6, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6653901Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.Type: GrantFiled: January 9, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventor: David A. Sobel
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Publication number: 20030217115Abstract: A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.Type: ApplicationFiled: May 9, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventor: Joseph B. Rowlands
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Publication number: 20030217216Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.Type: ApplicationFiled: October 11, 2002Publication date: November 20, 2003Applicant: Broadcom Corp.Inventor: Joseph B. Rowlands
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Publication number: 20030217238Abstract: A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.Type: ApplicationFiled: April 15, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventors: Joseph B. Rowlands, Koray Oner
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Publication number: 20030214982Abstract: A system for adding a time stamp to transmission traffic on a network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.Type: ApplicationFiled: October 30, 2002Publication date: November 20, 2003Applicant: Broadcom CorporationInventors: John Lorek, David R. Dworkin
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Publication number: 20030217236Abstract: A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first node is configured to fetch the coherency block from another node. The other node is configured to record a state in which the coherency block is provided to the first node. The first cache is designated to store the state of the coherency block recorded by the first node.Type: ApplicationFiled: October 11, 2002Publication date: November 20, 2003Applicant: Broadcom Corp.Inventor: Joseph B. Rowlands
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Publication number: 20030217235Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.Type: ApplicationFiled: May 9, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventor: Joseph B. Rowlands
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Publication number: 20030217234Abstract: A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is transferred responsive to transmission of the address on the interconnect. The system further includes a second interconnect to which the plurality of nodes are coupled, wherein ownership of a coherency block is transferred on the second interconnect responsive to a transmission of the data comprising the coherency block on the second interconnect. A first node of the plurality of nodes issues a coherency command on the second interconnect to fetch the coherency block in response to the transaction on the interconnect within the first node, whereby ownership transfers within the first node prior to ownership transferring from another one of the plurality of nodes to the first node.Type: ApplicationFiled: October 11, 2002Publication date: November 20, 2003Applicant: Broadcom Corp.Inventor: Joseph B. Rowlands