Abstract: Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. signal crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: Raster display memories are often arranged to output groups of pixels in progressive blocks, each having a plurality of pixels and each pixel having a plurality of fields. The fields in each pixel may provide color, overlay and cursor information for an individual position on a video screen. The numbers of bits in each pixel and in each field may be variable in different applications. In this system, control information indicates the starting position of each block, the location of each pixel in each block and each field in each pixel and the width of each pixel and each field in number of bits. Using this control information, the system recovers the pixels in each block and the fields in each pixel and processes such information to provide a display of the pixel information on a video screen. The number of bits contained in each field may be expanded to a width (e.g. 8) when the field width is less than eight (8) bits.

Abstract: A digital value represented by binary signals is converted to a corresponding analog value by three (3) current cells, preferably C-MOS p-type, in a digital-to-analog converter (DAC). The three (3) transistors, preferably disposed on an integrated circuit chip, comprise (a) an input switch transistor receiving a digital input signal at its gate, (b) an output transistor providing an output current at its drain and (c) a current bias transistor. The switch and output transistor sources and the bias transistor drain are common. The output transistor gate is biased by a substantially constant voltage. The bias transistor source receives a supply voltage through a bonding pad on an integrated circuit chip and a bond wire extending from the pad to a pin on the chip package lead frame. At low frequencies (e.g. 100 MHz), the wave shape of the output transistor drain current is flat. At increased frequencies (e.g.

Abstract: First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one control circuit to produce increases in the voltage drop across an impedance (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor device) closes to produce a first resultant voltage. The resultant delay in the third switch closure is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit, causing a second resultant voltage to be produced at a fourth switch (e.g. semiconductor device).

Abstract: Analog signals representing individual digital values (+3, +1, -1, -3) of data pass through a telephone line to a receiver. These signals may first be provided in a pseudo random sequence. A linear echo canceller and a first adder at the receiver simultaneously eliminate, to some extent, echo signals resulting from second analog signals transmitted through the telephone line by the receiver. A non-linear echo canceller and a second adder further significantly reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. In one inventive embodiment, each echo canceller includes a memory which stores, for each terminal in such echo canceller, data representing (a) the pseudo random sequence and (b) coefficients for adjusting the signals in such sequence. Such data for each terminal in such echo canceller is recorded in the memory for introduction to the next terminal in the memory.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: A system on an integrated circuit chip for providing a digital-to-analog conversion includes a plurality of output members each providing a particular current when energized. These members may be disposed on the chip in a pair of spaced columns. First control lines in the space between the columns of output members provide a thermometer code. Second control lines in this space provide a binary code. The first and second control lines are preferably parallel to the columns. When a first one of the first control lines is energized, different ones or combinations of the second control lines provide progressive values in the output members between "0" and "15", assuming four (4) of the second control lines. Similarly, when a second one of the first control lines is additionally energized, different ones or combinations of the second control lines provide progressive values between "16" and "31" in associated output members. At the same time, the output members providing a value of "15" continue to be energized.

Abstract: First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of the n-type with substantially identical characteristics. The input signals may be introduced to the gates of these transistors and the resultant currents may be produced at the drains of these transistors. Third and fourth transistors may receive the resultant currents. The third and fourth transistors may be CMOS transistors of the n-type with substantially identical characteristics. The resultant voltage at the first transistor may be introduced in a modified form to the third and fourth transistors to regulate the resultant voltage introduced to the third transistor and to expedite the response of the fourth transistor.

Abstract: A display memory respectively stores, in first and second portions, digital graphics data for display in a video monitor and digital video data for display in a window in the monitor. The digital video data is transferred from the display memory to a shift register at a rate different from the pixel clock and from the shift register at a clock rate that may be lower than the pixel clock rate. The video data may be stored in a luminance and chrominance format and may be converted by a color space converter to 3 bytes representing the primary colors red, green and blue. The video pixels may then be interpolated to expand the number of video pixels. The shift register operation may be synchronized with such expansion so that data is not passed from the shift register until the expansion of previous data from the shift register has been completed.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: In first and second modes, successive pairs of bytes, each with a suitable number (e.g. 8) of binary indications, are respectively processed in each clock cycle or clock half cycle to provide a true color. In these modes, the successive pairs of bytes may be processed in a 5,5,5, or a 5,6,5 pattern representing the primary colors for a pixel. In a third mode, the bytes may be introduced to a memory having a plurality of positions for storing individual binary combinations, which may be updated by a microprocessor, representing pseudo colors. In the third mode, a particular position in the memory is selected in accordance with the indications in each byte in each clock cycle or half cycle. In an additional mode, three successive bytes in a group may indicate the primary colors defining a true color when the fourth byte in the group provides a particular indication (e.g. 0 for all 8 binary bits).