Abstract: A system converts PAL and NTSC pixel clock signals to signals (in a studio, digital or square pixel format) at a sub-carrier frequency individual to the PAL and NTSC formats. The system includes a first register for providing a particular increase in the register count upon each occurrence of a pixel clock signal. Any remainder in the first register upon the production of the output signal is introduced to the register upon the occurrence of the next pixel clock signal. The particular increase in the first register count is controlled by a value in a second register, this value being adjustable dependent upon the system format and mode. A sequence of registers may be substituted for the first register with each register receiving an output from the previous register in the sequence. The system also converts signals representing the primary colors to luminance and chrominance signals.
December 9, 1993
Date of Patent:
January 3, 1995
Keith A. Jack, Douglas D. Moran, David J. Wicker
Abstract: A system provides a uniform delay in crossovers in opposite directions of a variable input voltage relative to a reference voltage. A comparator is included for producing first and second comparison voltages in accordance with the relative magnitudes of the input and reference voltages. A clamping circuit provides first and second clamping voltages. A control circuit produces first and second control voltages dependent upon the individual occurrences of the first and second comparison voltages. The first control voltage is greater by a particular magnitude than the first clamping voltage. The second control voltage is less than the second clamping voltage by the particular magnitude.
Abstract: Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal.
Abstract: A static RAM cell having first and second differentially connected lines reads binary information stored in the cell by providing a current through the cell and the first line to read a binary "1" or through the cell and the second line to read a binary "0". First and second transistors in a pre-amplifier respectively connected in the first and second lines provide outputs respectively representing a binary "1" and a binary "0". The first and second transistors pass control currents respectively through third and fourth transistors to produce bias currents in one of the first and second transistors when reading currents are not passing through that transistor and the cell. The control of the third and fourth transistors increases the frequency at which information is read from the cell and is amplified. In this improvement, the bias current in the line providing an output at each instant is reduced by respectively providing a negative feedback from the outputs (e.g.
Abstract: First binary bits are read synchronously relative to clock signals (e.g. 125 MH.sub.Z) from first memory positions and second binary bits are read from, or written in, second memory positions asynchronously relative to the clock signals without affecting the reading of the first memory bits. For synchronously reading the first bits, a plurality of channels are sequentially activated at a suitable frequency (e.g. 25 megahertz). Information from pairs of data lines are introduced into a pair of buses at the clock frequency. The information in the buses is sampled upon the occurrence of the first polarity in synchronizing signals having frequency (e.g. 62.5 MH.sub.3) derived from the clock signals and is prolonged and evaluated in a first pair of output lines upon the occurrence of the second polarity in the synchronizing signals. The information being evaluated is introduced to such output lines during the occurrence of the first polarity in the synchronizing signals.
Abstract: Input signals provide binary coded information at a first frequency. A ping-pong arrangement has two (2) substantially identical circuitries. The circuitries operate respectively in synchronism with first and second clock signals each having a frequency half that of the first frequency and each having a phase opposite to the phase of the other. When the first clock signal has a first polarity, the first circuitry produces first voltages representing these signals. In the second polarity of the first clock signal, the first circuitry produces first output signals representing the first voltages. The first circuitry continues producing the first voltages in the clock cycle after the initial production of such voltages. Similarly, the second circuitry produces second voltages representing the input signals in the first polarity of the second clock signal. In the second polarity of the second clock signal, the second circuitry produces second output signals representing the second voltages.
Abstract: Amplifying circuitry for use in a random access memory includes first and second input lines and receives complementary differential signals which respectively represent a binary "1" and a binary "0". The differential signals are respectively applied to first and second transistors connected to provide a rejection of the common mode in the differential signals. Third and fourth transistors also respectively receive the differential signals on the first and second lines. The third and fourth transistors operate as cascode transistors to respectively provide outputs on first and second output lines in accordance with the amplitudes of the signals on the first and second input lines. Fifth and sixth transistors are respectively connected to the third and fourth transistors to limit the currents through the third and fourth transistors.
Abstract: A comparator indicates the relative magnitudes of input and reference signals with improved immunity to noise signals. The comparator includes first and second transistors differentially connected to receive the input and reference signals. Third and fourth transistors connected in a latching relationship are responsive in first alternate half cycles of clock signals to the outputs from the first and second transistors to provide a regenerative action on these outputs. In first portions of the first alternate half cycles of the clock signals, a degenerative action is provided by fifth and sixth transistors respectively on the third and fourth transistors to prevent the third and fourth transistors from regenerating until the input difference voltage of these transistors has had time to increase relative to the input noise on these transistors. The fifth and sixth transistors may be provided with sizes corresponding to, or preferably sightly greater than, those of the third and fourth transistors.
Abstract: A system for regulating an output voltage to a particular value includes a control transistor which produces an output voltage when energized by an energizing voltage. A voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage.
Abstract: First circuitry on an integrated circuit chip has an input terminal, preferably the only input terminal, for receiving a voltage pulse introduced to a first terminal on the chip. The first circuitry damps the negative voltage peaks of the voltage pulse at a voltage of a first magnitude inherent in the construction of the first circuitry. A pair of input transistors in the first circuitry have dimensions to provide, at the input terminal to second circuitry, a clamping voltage of a first magnitude at a certain fraction of the power supply voltage. The first circuitry may include a closed loop servo amplifier which regulates the negative peaks of the pulse at the input terminal to the second circuitry to a value approximately equal to the voltage of the first magnitude. The second circuitry compares the negative peaks of the input voltage pulse with a voltage of a second magnitude inherent in the construction of the second circuitry to provide an output logic pulse.
Abstract: A code parser decodes coded compressed image information into an intermediate code. A code expander operating asynchronously relative to the code parser decompresses the compressed image information in accordance with such decoded information. A window register in the code parser has a length at least as long as the longest code in the intermediate code. When the intermediate code indicates a pattern in one line in a raster scan of an image corresponding to a pattern in an immediately preceding line, the window register and associated circuitry scan the one line and provide for the decompression in such line in accordance with the decompression at the corresponding positions in the preceding line. Such associated circuitry may include two memories, one for even scan lines and the other for odd scan lines. Alternate ones of the memories are activated for information comparison between adjacent lines during alternate line scans.
December 21, 1989
Date of Patent:
December 8, 1992
John E. Nelson, Gerard J. Papa, Teddy W. Berwin
Abstract: A first switch (e.g. semiconductor) becomes conductive when at least one of two binary inputs to be added is a binary "1". A second switch (e.g. semiconductor) becomes conductive when there is a carry of a binary "1" from a preceding stage. The semiconductors provide a particular potential on an output line when both semiconductors are conductive. This potential provides a binary carry to a carry switch in the next stage. The carry switch in the next stage is an n-channel semiconductor when the carry switch in the previous stage is a p-channel semiconductor. A logical network also produces a signal when both of the binary inputs are a binary "1". This signal causes a third switch (e.g. semiconductor) to become conductive and to produce the particular voltage on the output line whether or not the particular voltage is produced on the output line by the operation of the first and second switches.
Abstract: A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first display line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines.
Abstract: A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a line for providing a negative biasing potential. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line.
Abstract: Apparatus converts into an analog value signals representing digital values. Sub-sets of switches are provided, the number of switches in each sub-set being directly related to the digital significance of the switches in such sub-set. The switches in each sub-set may be paired to provide for a conductivity of one switch in each pair. The signals representing individual digital values are introduced to the associated sub-sets to provide for the conductivity of an individual one of the switches in each pair in accordance with the digital value represented by such signals. The switches are connected in a recursive relationship defined by repetitions of a basic block. Each basic block is in turn defined by a pair of basic sub-blocks. A plurality of capacitors are also provided as output members. The capacitors are connected to the recursive relationship of the switches to charge the capacitors through paths defined by the conductive ones of the switches.
Abstract: A balanced cascode current mirror includes first and second current paths respectively defined by first and second transistors and by third and fourth transistors. Each current path may include the sources and drains of the transistors in such path. Connections may respectively extend between the gates of the first and third transistors and between the gates of the second and fourth transistors to provide the first and third transistors with substantially identical source, gate, and drain impedances. An input current is introduced to the drain of the second transistor and an output current with substantially identical characteristics is obtained from the drain of the fourth transistor. A capacitance may be connected between the drain of the second transistor and the gate of the first transistor to produce a flow of current at high frequencies through the first current path corresponding to the input current at the drain of the second transistor.
Abstract: First terminals are equally spaced on a substantially uniformly resistive thin film at or near a first side edge of the film at progressive positions downwardly from the top of the film. Near the bottom of the film, second terminals are preferably equally spaced progressively inwardly from the first side edge of the film. An energizing potential is applied to the film either at the corner defined by the top and the first side edge of the film or in a curved pattern of positions near such corner. A reference potential (e.g. ground) is applied to the film near the otherside of the film and near the bottom edge of the film. Voltages are thus produced at the successive ones of the first terminals with an exponential relationship with respect to such terminal positions and at the successive ones of the second terminals with a linear relationship with respect to such terminal positions. The disposition of the second terminals may be compensated for deviations in a logarithmic response in an output member (e.g.
Abstract: A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g.
Abstract: A plurality of equally spaced terminals may be disposed at a side edge of a substantially uniformly resistive thin film. A reference potential (e.g. ground) may be applied to the second side of the film. An energizing voltage may be applied at the juncture between the first side edge and a particular one of the top and bottom edges of the film. In this way, the successive terminals receive voltages with a logarithmic relationship relative to the terminal positions. When a linear relationship of voltages is desired at successive terminals in a low range, no reference potential is applied to the second side edge of the thin film. Instead, the other one of the top and bottom edges may receive the reference voltage. Alternatively no reference voltage may be applied and terminals indicating the linear voltages may be disposed at such other edge.
Abstract: A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude.