Abstract: A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a plurality of microprogrammed execution units (EAD, BDP, FPP) communicating with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BDP). A third unit is a floating point calculation unit (FPP) to permit the units to function autonomously, each unit includes its own command block and synchronizing means, for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit.Each command block includes means for commanding instructions for triggering the execution of the microprogram of the first instruction in standby.

Abstract: The method relates to the generation of interfaces that are structured around a window and can be displayed on the screen of a data processing system working in the graphics mode. The method is characterized in that a survey module is associated with the items incorporated in the interface, the module being arranged for displaying, in at least one survey window (16), an instantaneous synoptical table (18, 20) representing the constitution of all or part of the interface and composed on the basis of a descriptive status of the items (22), and that in the interactive mode, the creation and/or modification and/or incorporation of the items (22) is performed with the aid of at least one working window, preferably of the dialog window type, under the instantaneous control of the survey module. The invention also relates to an apparatus for performing this method.

Abstract: A device for fast memory access in a computer system that employs a high-speed associative memory for storing extracts that each include an address and an associated information element. Each extract is associated with a presence flip-flop and a reference flip-flop, their respective states being changed when an extract is used. The device according to the invention is designed to operate using two clock phases. During a first clock phase, the device compares an address to be translated with each address contained in the high-speed associative memory, evaluates a saturation condition, and latches the result of this evaluation. During the second clock phase, the device updates reference indicators as a function of the coincidence signals which are latched during the first phase and of the latched evaluation signal. The invention can be used in conjunction with cache memories and for translation of virtual addresses to real addresses.

Abstract: A method for transferring an element of binary information of the differential type present on two first bit lines to two second bit lines through a differential amplifier. The method includes a precharging phase followed by an evaluation phase of the first bit lines. The precharging phase consists of short-circuiting the first bit lines to each other and short-circuiting at least one of the second bit lines to the first bit lines. Such a differential amplifier may be utilized in an electronic circuit and assembly such as a carry select adder circuit.

Abstract: A method of data transmission over an internal bus of a workstation, effecting communication of an interface coupler and a telephone line and devices adapted for various communication functions. The method employs the synchronization signal of a voice network to define 125-microsecond communication frames. Included in each 125-microsecond frame thus defined are a maximum of eight variable-length subframes corresponding to a maximum of eight devices. The first two bytes of each subframe are header bytes. Coded in the header bytes of each subframe are a device destination address, and length codes indicating the number of bytes of data included in the subframe and the number of active bits in the last byte.

Abstract: A protected method of fast writing of information for at least one mass memory apparatus (DMM.sub.1) belonging to an information processing system including at least one central host (H.sub.1, H.sub.2), two control units (UC.sub.1, UC.sub.2) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) connected to a first and second parallel bus (B.sub.1, B.sub.2) is disclosed wherein the method is characterized in that, if the host (H.sub.1, H.sub.2) is connected to each of the two buses via at least one first host adaptor (HA.sub.1, HA.sub.2) belonging to the first control unit (UC.sub.1, UC.sub.2) and the mass memory (D.sub.1 -D.sub.5) is connected to each of the two buses via a first and a second mass memory adaptor (DA.sub.1, DA.sub.2) belonging to the first and second control unit, respectively, which include a first and a second memory buffer (MTD.sub.1, MTD.sub.2), respectively,I--the block of data to be written is memorized in the first host buffer (MTH.sub.1, MTH.sub.

Abstract: The state of conduction of an MOS transistor 11 is definitively controlled by a laser beam 21, by forming an electrical connection 22 between the gate 16 and the subjacent portion d of the source region 14 or drain region 15. The invention is applicable in particular to the correction (reconfiguration, redundancy) of integrated circuits and to the programming of integrated PROMs.

Abstract: A multifunctional coupler for connecting a central processing unit of a computer to one or more peripheral devices and for storing at least one portion of an application microprogram that is operative to control transfer of data between a peripheral and the CPU. The coupler includes a mother-board with at least a first and second interface for connecting an output bus of the CPU to at least first and second daughter-boards, respectively. The mother-board also includes a control and command microprocessor that is connected to both the first and second interfaces, a RAM and a first ROM, all connected to an output bus of the microprocessor. The daughter-boards each include a second ROM for storing an application microprogram that includes a first program segment common to all application microprograms run by the microprocessor, that is read from the first ROM, and a second segment that is read from a second ROM, the second segment being specific to a particular application executed by a peripheral.

Abstract: A computer and method that can be used in digital computers to calculate the inverse I of a number D. The inverse is approximated by I2 after the application of a complementary correction Cjl to an approximation I1 obtained by linear approximation on the basis of a first value Io which in turn is obtained on the basis of an inverse table. The correction value Cjl is obtained from pre-established data CBl and Hj that are memorized in tables of reduced dimensions.

Abstract: The digital data transmission is of the type including the addition of clock and synchronizing information to the data to constitute the transmission signal, and the determination of the transmission speed from this received information. According to the invention, this information, in the transmission signal, comprises a synchronizing edge (SYNC) added to each group of N data bits (D0-D7, OP), and the determination of the transmission speed comprises producing N clock signals (CL0-CL9) from identical successive delays (480-489) of a synchronizing edge detected.

Abstract: A frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shift signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: The package (10) of the integrated circuit (11) includes a TAB carrier (12), the supply conductors (15b) of which comprise shielding elements between groups of signal conductors and have a length that is largely shunted via a corresponding potential conductor plane (26b) of the decoupling device (24) of the package.

Abstract: A garbling method for 9 non-coded matrix keyboard, and the circuit for performing the method. includesa) connecting at the output each row and column of the keyboard to the outputs of a first register (160) of a parallel to the outputs of a first register (160) of a parallel input-output interface (16), via a circuit (163, 166, 164);b) connecting each row and column of the keyboard to the individual inputs of a second register 162 of the input-output interface.c) randomly setting the order in which the outputs of the first register will be scanned;d) setting at least one of the outputs of the first register at "1" and checking whether one of the corresponding inputs of the second register is at "1";e) if not, scanning the remaining lines one by one by placing them each at "1" until the associated input is at the value "1";f) repeating steps d) and e) to determine the column or row respectively, corresponding to the key of the keyboard that has been depressed.

Abstract: A process of authentication, by an outside medium, of a portable object connected to that medium via a transmission line and a system for carrying out the process. To authenticate a portable object (7) connected to a terminal linked to the outside medium by a transmission line, the outside medium (1) manages a control table (11) containing a non-secret piece of data (N.sub.7) specific to each object that can be identified, as well as a parameter (E.sub.a ) and a result (R.sub.a) entered in the control table during the preceding authentication of the object. A new parameter (E.sub.b), produced by the medium during authentication, is used to calculate a new result (R.sub.b) in the object. The old result is recalculated. If it matches the one in the table (11), the object is authenticated, and the new parameter (E.sub.b) and result (R.sub.b) are entered in the control table in place of the preceding ones. The process is well suited for use in protecting computer networks.

Abstract: The present invention relates to a method of assembling a monitor tube on a front frame, to the monitor thus obtained, and to the assembly machine. The method of assembling the monitor tube on the front frame of the monitor includes the following steps:a) placement of a front frame in a housing;b) blowing air through a nozzle to maintain the tube (105) in suspension;c) centering the tube (105) by way of two V shape support blocks (501, 521) displaced concentrically and simultaneously;d) reversing the direction of air through the nozzle to place a suction on the tube (105) and opening of the V shaped support blocks (501, 521);e) lowering of the tube (105) while connected to the suction to place it into contact with zones (1024) having a high coefficient of adhesion;f) joining the tube solidly to the front face (102);g) stopping the air flow to terminate the suction and release the assembled set.

Abstract: The invention is in the realm of an information processing system including a central unit which includes several processors sending requests to several processors sending requests to several memories via an input interconnection and receiving responses from those memories via an output interconnection. To simplify the input interconnection when the number of processors and memories increases, a ring of stations equipped with a register is used. A request given by a processor is loaded into a station when that station is free or becomes free, If not the ring functions a fed back shift register. A station becomes free when the request contained in the station downstream is accepted by a memory. An analogous device can be used for the output interconnection. A notable application is vector processing.

Abstract: A data processing system is presented, comprising at least one central unit (CPU), at least one central memory (MMU), and internal communication bus to which the CPU and MMU are connected, at least one peripheral unit, a control module (IOM), and an external communication bus to which the peripheral unit and the control module are connected. In this system, the IOM is also connected to the internal communication bus. The internal and external communication buses are of differing types. Within the IOM, the connection to the internal communication bus is via an internal interface device (CLM), while the connection to the external communication bus is via an external interface device (PLM). An inter-device interface (PLI), also within the IOM, connects the CLM and PLM, so as to adapt the protocols of each to the other.

Abstract: A precharging circuit of a memory bus that includes a bipolar transistor driven by a clock signal wherein the base of the bipolar transistor is connected to both supply potentials through two respective complementary field effect transistors having their gates connected to the output of a threshold amplifier connected to the bus. The precharging circuit allows adjustment of the precharging voltage of a memory bus to a value predetermined during the precharging phase of the clock signal.

Abstract: The present invention relates to an arrangement for protecting an electronic card and to its use for protecting a terminal for reading a magnetic card and/or a microprocessor card. An arrangement for protecting a card including, on a printed circuit, an electronic circuit with volatile memory (12) containing programs or information to be protected, characterized in that it includes a resistive network (21, 22) surrounding the circuit (1) embedded in the resin (3), the resistive network (21, 22) being incorporated in an electronic circuit (10) for detecting modifications to the resistance of the network, to bring about a destruction of the information of the volatile memories (12).

Abstract: A gateway device for connecting a computer bus to a high-speed fiber optic ring network including an I/O host module of the computer connected to the computer bus and having at least one external communication bus for carrying both data and control blocks containing parameters relative to the composition of data frames. The gateway device also includes an adapter device physically connected to the network, and an interface which ensures transfer of the data and control blocks between the I/O host module and the adapter device. The adapter device includes a memory for storing the data frames before they are transmitted to the network and after they are received from the network, and a transfer management controller for managing the transfer of data frames between the I/O host module and the network. The controller includes a control bus which carries the control blocks and the control characters of the data frames. The adapter device further includes a high-speed bus which transports the data.