Abstract: The invention relates to the field of data processing systems and provides a method and system to enable replacement of memory modules (MU.sub.i) connected to a bus (MB) without interrupting the functioning of the system, wherein for any writing request addressed to a module to be replaced (MU.sub.i), this writing request is executed simultaneously and at the same address by the module to be replaced (MU.sub.i) and by a replacement module (MU.sub.r), and for any reading request addressed to the module to be replaced (MU.sub.i), only the module to be replaced (MU.sub.i) is authorized to execute this reading request. Next, a recopying process is started which includes sending reading and rewriting requests to a set of addresses covering the entirety of the memory space of the module to be replaced (MU.sub.i).

Abstract: Via studs (23) of the multi-layer structure (12) are formed on a uniform metal layer that is subsequently etched to form the conductors (17) of a conductive layer of the multi-layer structure.

Abstract: A protective wrapper is provided that is especially well suited for packaging heavy products held by gripping elements during a packing phase. The protective wrapper is completely closed on three sides and is partially open on a fourth side that includes a passage means, e.g., a simple cut. The passage means makes it possible to first insert the product to be packaged into the wrapper while the product is held by a gripping element, and then to release the gripping element once the wrapper is in place around the product. The protective wrapper also includes a gripping means that facilitates extraction and holding of the wrapped product during its unpacking. A method for packaging that employs the wrapper is provided which can easily be automated.

Abstract: The conductor 15 to be connected to the doped region 12 of the substrate 11 has an edge 15a at which the laser beam 20 is aimed, regulated such as to definitively create a zone of low electrical resistance 19 in the dielectric layer 13 that separates the conductor from the doped region. The invention is particularly applicable to programming by laser of read only memories and defective integrated circuits with a view to correcting them.

Abstract: A station (ST) of a multi-station ring communications network (RN), wherein data are transmitted in a predetermined direction includes a frame receiving device (DRX) for frames received from the ring, and a frame transmission device (DTX) for transmission of frames to the ring. The station (ST) further includes a FIFO repetition memory (ERPT), disposed in series between the reception and transmission devices, wherein the reception device (DRX) decides whether the frames coming from the ring should be either destroyed or repeated and subsequently sent to the repetition memory (ERPT). The transmission device (DTX) transmits the frames contained in the repetition memory or the frames proper to the station, by deciding whether the station has the right to transmit as a function of the contents of the repetition memory.

Abstract: An information processing system architecture (ORDI), in which the various constituent elements (B.sub.1 -B.sub.6, A.sub.1 -A.sub.6, C.sub.1 -C.sub.4) comprise a plurality of boards (CDI.sub.i and CGI.sub.j), each embodied by printed circuits carrying a plurality of integrated circuits, and including at least two sets of elements (ENSI.sub.1, ENSI.sub.2), all or some of the elements of one set being identical to all or some of the elements of the other. The sets are associated with two system buses of the parallel type (PSBA, PSBBI) that assure both communications and the transfer of data and electrical energy among the boards. The two buses have a total or partial overlap zone (ZC) between them, on which either one or more elements (C.sub.1 -C.sub.2, C.sub.3 -C.sub.4) common to the two sets exclusively, and elements belonging to the first set (ENSI.sub.1, A.sub.5 and A.sub.6) and/or to the second set (ENSI.sub.2, B.sub.5 and B.sub.6), are connected.

Abstract: A method and apparatus for fast memory access in a computer system employing a high-speed associative memory for storing extracts that each include an address and an associated information component. Each extract is associated with a presence indicator and a reference indicator, their respective states being changed when an extract is used. According to the method of the invention, the state of each reference indicator can be changed only if the number of extracts present is at least equal to a threshold value. The invention also relates to apparatus for implementing the method. The invention can be applied to cache memories and to translations of virtual addresses to real addresses.

Abstract: An integrated circuit includes parallel processors and is used for spoken word recognition. In order to provide a local equation which is programmable, a general purpose calculating processor includes a bank of registers, which bank is modified in configuration depending upon the values in a general mode GMOD register.

Abstract: A method for obtaining at least one securitized cleartext attestation by at least one requestor subject coupled to a data processing system and communicating with each other through a network. The data processing system includes a plurality of subjects and an authority represented by at least one server acting on behalf of the authority and issuing attestations. The requestor subject sends the authority an attestation request including at least one protection datum. The requestor subject chooses, at random, a check datum which is associated and linked with the protection datum. The requestor subject then transmits, in cleartext, to the authority both a piece of identification information defining the relationship between the check datum and the protection datum, and the protection datum itself. The server organizes the attestation in the form of binary information and calculates at least one of a signature and a seal of attestation taking into account the protection datum and the identification information.

Abstract: A communications controller is provided that allows transfer of a large number of frames to each of the channels of an S.sub.0 -type link to be handled simultaneously at a data transfer rate matched to that of the link. The communications controller is connected between a bus associated with at least one host computer and the terminals of a network connected by a time-multiplexed digital link. The communications controller includes a base unit connected to the bus for managing and effecting the transfer of frames for the link, and a peripheral unit connected to the base unit and to the network.

Abstract: The invention relates to a method for inspecting a populated printed circuit board, particularly for inspecting the solder joints on the board, and advantageously usable for boards populated with surface-mount (SM) components. According to the invention, the inspection method comprises at least the following steps:briefly heating the board (or an extensive portion thereof),recording a thermographic image of the board (or of said extensive portion) when said heating step has stopped, and preferably as soon as it stops,analyzing the image by detecting a difference in heat between a predefined standard and the areas of the board to be inspected, for example the soldered areas.The invention also relates to a system for working the inspection method.

Abstract: The invention pertains to electronic data processing systems including a plurality of removable units that communicate with one another via a bus. To enable disconnection or connection of the removable units without interrupting the operation of the system, each unit includes first means (4) controlled selectively by a maintenance device, to assure the functional isolation of the removable units. The system further includes second means (8, 1B) capable of causing the reception devices (1) of the units to function by a mode that procures increased immunity to interference for them.

Abstract: Tis termination adaptor connector is provided to receive bulky adaptation and/or simulation elements (4) when there is limited space for the connector and comprises a flexible printed circuit (3) to carry the elements (4) and connect them to the connector (2). The linkage between the connector (2) and the circuit (3) is obtained by means of slit self-stripping connections (6) carried by the same connector, which lock the conductive ends (31) of the circuit (3) in associated slits (60). The entire assembly can then be contained inside a small housing.

Abstract: A peak clipping circuit for an integrated circuit of the VLSI type is connected in parallel with the integrated circuit and includes a peak clipping transistor of the bipolar T type and a charge transistor M of the MOS type. The charge transistor has its gate connected to an input of a circuit device of the integrated circuit. The clipping circuit functions to minimize parasitic oscillations at the working level of the input signal.

Abstract: A time constant circuit for regulating the phases of clock signals of a synchronous system includes a plurality of transfer gates composed of MOS-type transistors whose drain-source leads constitute resistance elements. The time constant is adjusted by selectively activating transfer gates, the capacitance of the circuit being the total structural capacitance of the MOS transistors. To ensure that the capacitance remains constant, each transfer gate is associated with an auxiliary compensating circuit which, when activated, introduces a capacitance of the same value as the capacitance of the gate in the conducting state. The invention likewise relates to a variable-delay circuit using the time constant circuit.

Abstract: An ISDN multiprotocol communications controller for controlling a communication link of thte S.sub.2 type (LS.sub.21 to LS.sub.24) between a computer (COMP) and a set of terminals (T.sub.1, T.sub.2, . . .) through an automatic telephone branch exchange (PABX) comprising a basic controller (UEI) controlling the higher communication layers of the OSI model and a peripheral device (UPRI) executing the control of communications between the computer (COMP) and the other terminals, as well as the multiplexing and demultiplexing of the data channels of the link. The controller includes, in series, a dynamic allocation device (DADI) allocating the time channels (VT.sub.i, VT.sub.j) corresponding to the data channels, executing the concentration of m time channels of the link in n physical channels (with m>n) of a dual-access memory (DAMI) of the FIFO type, in transmission and reception, and a signal processor (PCSI) connected to a programmable memory (MMI.sub.

Abstract: Turns of primary and secondary windings of a chopper power supply transformer are formed by magnetically coupled stacked parallel planar printed circuit conducting layers. The primary winding is between first and second parts of the secondary winding that are connected in series and parallel. Layers at opposite ends of the primary winding are (i) arranged to reduce leakage currents between the secondary winding parts and (ii) positioned between further layers of the primary winding and the secondary winding. Terminals of the first and second layers are connected together as a first input terminal of the transformer. Other terminals of the first and second layers have a common connection. Further layers of the primary winding are connected in series with each other between the common connection and a second input terminal of the transformer.

Abstract: A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.

Abstract: A central unit for a data-processing system having a high degree of parallelism. This central unit includes a number of basic processors sending requests to a number of modules in receiving responses from those modules. To simplify the interconnection between the modules and the processors when their number increases, the invention is characterized wherein the requests sent from each processor are transmitted to the input of each of said modules via an input shift register, wherein the response coming from each of the said modules are transmitted to the input of each processor via an output shift register, wherein for any provided processor, the number of stages of said input shift register making it possible to access the modules is different for each of the modules and wherein for any processor, the total number of stages belonging to the input and output shift registers associated with one of the said modules is constant and independent of the module and processor in question.

Abstract: A method for authentication by an external medium of a portable object such as a standardized credit card coupled to this medium. The portable object (2) calculates a result (R) which is at least a function of a secret key (S) and of a variable datum (E). This result (R) is sampled by the external medium (1), which compares it with a reference result (RO). This result (RO) is changed in a random manner, by being replaced by a new result (RO) calculated by a portable object (2) which has been authenticated based on the preceding reference result.