Abstract: A tool (KD) for debugging an operating system, which among other elements includes at least one processor (P), a memory (M) for use by the processor, and a memory management unit (MMU). The tool is stored in a zone of the memory (M) where the virtual addressing mode is equal to the physical addressing mode. The tool is operable to perform by a predetermined method, and the tool executes each operation in the physical addressing mode, independently of the management unit (MMU). For controlling the phases of initialization of the machine, the tool supports at least two exception vectors (BP, DSI), and among other elements includes its own stack (S), a decoder (DEC) which uses an algorithm that is operational regardless of the context of the process analyzed and regardless of the storage means (CMM) of the decoded context.

Abstract: This method for administration of an information processing resource by an arbitrary administration system (MAN) allows the management of any arbitrary application (APP) whose symbols table (ST) is contained in the executable program. To achieve this, an agent (AGE) is created in conformity with the standard administrative protocol (SNMP), this agent being parametrizable by means of the configuration file (CF) that the agent contains. Once the agent has been created, the agent (AGE), by way of the symbols table (ST), on the one hand, which provides the correspondence between the name of a variable and its implantation in memory, and by way of a system function call (SC) of the analysis process type, on the other hand, directly accesses the memory zone where the implantation is provided by the symbols table ST, to enable the proper processing operation as a function of queries from the administration system (MAN).

Abstract: An integrated circuit (IC) includes a device (10) that adapts the impedance to the characteristic impedance (Zc) of transmission lines (13) each connecting a transmitter (11) to a receiver (12). Two adaptation blocks (14, 15) reproduce the respective structures of the transmitters (11) and receivers (12) and their impedance is adapted by a reference resistor (Rr). A closed loop control device (Len, Lep, Lrn, Lrp) reproduces the adaptation conditions in the transmitters (11) and receivers (12) respectively.

Abstract: A system for transactional processing between an information processing server (3) and a plurality of workstations (2) between which the jobs corresponding to activities constituting procedures are executed, the system including, on the server side, a scheduler module for scheduling the progress of the jobs; a dispatcher module (31) for performing the distribution of the tasks which are based on the relationship between a role and an actor; a signaler module (34) for preserving a trail of times events and receiving information from the scheduler (30) and from a coordinator module (31); a message box (35) exchanging signals on the one hand with the dispatcher (33) and signaler (34) modules, and on the other hand with a module (36) for communication with the workstations and a data management module for the work flow (370), the system including on the part of the workstation a communications layer (27), a message management layer (26) corresponding to the work flow, a layer (24) including various sets of interf

Abstract: The method of computing the reverse image of the transition function .DELTA.(.delta., .delta.') of a product finite state machine (PFSM): .DELTA..sup.-1 (E.sub.n-1) from the set of n-1 equivalent states comprises the steps of (a) constructing in a canonical way, from the BDD of the graph of the equivalence relation E.sub.n-1, the BDD of the graph of a total function from S into S, named cross-section and denoted C(E.sub.n-1), (b) constructing from the cross-section and vector .delta. a new vector .delta..sup.n-1 =C(E.sub.n-1)o .delta., and (c) computing the equivalent pairs of states with respect to the vector .delta..sup.n-1 to have the pairs of (.A-inverted.x.DELTA..sup.-1 (E.sub.n-1).

Abstract: A system architecture for enabling remote control of an application, including a first service processor connected via a network and a maintenance unit with channels (40) connected to a central system (4), in which the service processor (1) is connected via a service console switch (30) to a maintenance service console (RMS 6), and to a remote service console (RSC 5), wherein each service processor and each console further includes operating system programs, a supervisor program, and at least one service broken down into two applications, one called the "body", comprising the program algorithm, and the other, "presentation", including the interface with the user enabling a windows-type display with a menu bar.

Abstract: The subject of the invention is an integrated delay circuit (10), including two amplifiers (11a, 11b), furnishing different delays, and having a common input, and a control block (12) connected to two terminals of the two amplifiers, respectively, in order to vary the phase offset between the two amplifiers. This circuit is integrated into a III-V semiconductor, such as gallium arsenide.

Abstract: A process for analyzing deadlocks in an operating system of a machine uses a method which consists of searching, for any thread stopped on a lock, for the thread that holds that lock and when the thread itself is waiting for a lock, of going up the chain until a cycle is found. When the machine has a symmetrical multiprocessor and operates in a UNIX environment, this process makes iterative use of a specific function which makes it possible to go from one thread and from all the processors to any type of lock (active or passive waiting) by going through the threads one after the other to reconstruct a deadlock and hence a cycle, element by element. When a virtual memory is used such that all the necessary information is not in the physical memory, it also helps a user arrange all the chains provided by said process to reconstruct the cycle determining the deadlock.

Abstract: A buffer memory management method for a buffer memory consisting of a set (14) of buffers (15), using a list of buffers arranged by order of least recent use (LRU). The method comprises, when a buffer (15) is referenced, classifying the buffer according to its position (p) relative to a threshold list position (t). The threshold position is advantageously defined according to the current buffer access hit rate. The method is suitable for operating the buffer memory with concurrent local and non-local processing.

Abstract: A method for remote booting by a server of at least one terminal, including a volatile memory (RAM), at least one processor, a telecommunications card enabling connection to the server by a network, said server being provided with telecommunication device and memory of sufficient capacity to store the communications protocol, the operating system of the terminals recopied into an image file, its own operating system, and the applications programs, wherein the method includes the remote loading of a startup program by transforming the first interruption produced by a terminal following its being powered up into a request for reading an image file memorized in the server.

Abstract: A system of a maximum of N units (A, B, C, D, . . .) distributed in a network (RE) operating by a predetermined protocol (SCSI) by which the length of any bus (SCSI.sub.1, SCSI.sub.2, SCSI.sub.3) assuring the connection of a plurality of units among one another has a given maximum value, characterized in that, since the distance between the units is greater than the maximum value, it includes a plurality of local partial buses (SCSI.sub.1 -SCSI.sub.3) that are connected to one another via bidirectional point-to-point links (LPP.sub.1, LPP.sub.2) and are managed by intermediate transmission devices (DIT.sub.1, DIT.sub.21, DIT.sub.23, DIT.sub.3), each of which is connected both to a partial bus and to a point-to-point link and intervenes in the phases of gaining control of the network on the part of any unit connected to any one of the partial buses.

Abstract: A data transmission system between a computer bus and a large number of data storage units connected to one another by a specific connection to which the system is physically connected, including a central microprocessor running an operating system; and frame transfer capability including a data storage memory located between the bus and the connection. The operating system is associated with at least one application and includes at least one input/output microprocessor connected to the memory and to the connection. The application includes an initialization process; several adaptation processes each associated with a storage unit to adapt the protocols used on the buses and connection; and a task management process authorizing the input/output microprocessor to transfer the commands and the data corresponding to them from the memory to the connection and vice versa, on a message of the adaptation process.

Abstract: A system of at least one OSI transport relay ensuring cooperation between at least a first system containing at least one source system (SS), using an OSI transport profile based on a network service in connected mode, called CONS, and at least a second system including at least one target system (SD) using an OSI transport profile based on a network service in non-connected mode, called CLNS, with the information routed on the transport layer. According to the invention, the system characterized by the fact that the addresses of the transport service access points TSAP of the source and target system (TSAP.sub.S and TSAP.sub.D) are transported end to end by the transport layer, in connection requests TPDU-CR, and the addresses of the network service access points used by the network service are those of the source and relay systems (NSAP.sub.S and NSAP.sub.R). The invention is application to telecommunications networks.

Abstract: The invention relates to an address conversion process for porting a telecommunications application APP from the TCP/IP network to the OSI/CO network, and to an address conversion module used in this process. In a known manner, access to the networks is authorized by way of a "socket" interface (SOC) for the TCP/IP network, and an "XTI" interface for the OSI/CO network. In a notable manner, the "socket" interface calls (SC), like a plurality of system cells (SY), are in a first time period oriented, at the moment of the link editing phase prior to obtaining the executable, to a module (W) for automatic address conversion of the library type. This module (W) then performs the conversion of the addresses specific to the TCP/IP network into addresses of the OSI/CO network and enables the passage from the TCP/IP protocol to the OSI/CO protocol. After conversion, the calls are transmitted to the "XTI" interface and can be used directly in the OSI/CO network.

Abstract: The process for exchanges between the levels in a hierarchy of memories comprising at least one intermediate level in the hierarchy linked to a higher level in the hierarchy and to a lower level in the hierarchy, with each level in the hierarchy being divided into memories (3, 5, 6) which are in turn divided into blocks (10) containing information (11) associated with addresses (Ad), with the blocks of the memories on the higher level and on the intermediate level in the hierarchy containing copies of the information held in the blocks at the corresponding addresses on the lower level in the hierarchy, and during a modification of a piece of information in a block (10.

Abstract: A data transmission system coupled between a computer bus (PBS) and a network (RE) includes a coupling device (GPU) linked to the bus and communicating by an interface with an adapter device (DEA) including a microprocessor (CPU2) connected to the network, an initial microprocessor (CPU1), and apparatus for transferring frames from the bus to the adapter device including a double port. The system is characterized by the fact that the interface is constituted by command files (F1 to F4) grouped in the memory, the second management processor handling software modules (ML1 , . . . ML10) independent of each other, to manage the emission and reception of specific frames from the network and communicating by means of letter boxes (BAL1, etc . . . ) included in the second processor and/or command files.

Abstract: Data input/output device for the display of information which is monolithically integrated in an application specific integrated circuit (ASIC). The device is principally constituted by a single memory which is divided into specific zones for the programs, the screen and the character generator. Access to the various specific zones is authorized by a single-memory bus line MB and is administered in accordance with a sequencing method provided by a microprogrammed sequencer programmed for flow regulation. Various devices can be added to the ASIC to make it possible to fully utilize the pass band of the memory, such as cache memory (CM), a FIFO register (FR), and line buffer registers (RB).

Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: The memory (DAT) with blocks (BL) organized in N columns of n levels is managed by a method consisting of prohibiting access to blocks that are unusable because of operating defects, by associating the unusable blocks with a flag (F) advantageously incorporated into the addresses of the blocks. When these addresses incorporate at least two bits combined to indicate the states of the block at that address, the flag (F) may be a free combination of these two bits.

Abstract: A very high-level bidirectional protocol (CP) used for communication between a hypermedia system (HS) and a large number of interconnected editors (HSE, Ea, Eb, Ec, . . . ) communicating within a hyperstructure. This protocol (CP) uses a set of messages that allow each editor to manipulate and manage the contents of hypermedia objects called nodes, and it is also manipulated by the hypermedia objects and is accessible through a programming interface.