Abstract: A cold plate assembly includes a cold plate with at least two plumbing ports. The cold plate assembly further includes a spring plate assembly, which applies an actuation load to the cold plate. The spring plate assembly includes a spring plate and a spring pin moveable in a slot of the spring plate assembly to maintain the actuation load. The actuation load is configured to mechanically actuate the cold plate to a module.

Abstract: A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations.

Abstract: A system for estimating and generating project plans for implementing packaged software applications, the system includes: a view layer configured to act as a user interface for user inputs and system outputs; a model and control layer configured to implement rules based on a series of estimation and implementation models, and to perform calculations of project plan details and project plan schedules; an estimation knowledge base layer configured to hold and derive the series of estimation and implementation models; and wherein the system for estimating and generating multi-dimensional project plans for implementing packaged software applications is carried out over networks comprising: the Internet, intranets, local area networks (LAN), and wireless local area networks (WLAN).

Abstract: A photonic waveguide structure includes a first photonic waveguide layer located over a substrate. A sidewall cladding layer is located cladding a sidewall, but not covering a top, of the first photonic waveguide layer. A second photonic waveguide layer may be located upon the top of the sidewall cladding layer while contacting, but not straddling, the first photonic waveguide layer. The sidewall cladding layer protects the first photonic waveguide layer from environmental exposure, thus providing enhanced performance of a photonic waveguide structure. A planarizing sidewall cladding layer allows the fabrication of optical chips with multiple layers of lithographically defined devices.

Abstract: A method and apparatus for changing and adding activation keys for functions of digital content without having to change and recompile the digital content. The rules for validating activation keys, the code for providing instructions for executing the rules for validating the activation keys and a template for identifying possible activation keys, which keys are currently valid and validating rules associated with each currently valid activation key are separated and separately secured.

Abstract: Sequences of ribonucleic acid interference molecules are provided. For example, in one aspect, at least one nucleic acid molecule comprising at least one of one or more precursor sequences having SEQ_ID NO: 1 through SEQ_ID NO: 3,197 and one or more corresponding mature sequences having SEQ_ID NO: 3,198 through SEQ_ID NO: 6,565 is provided. Techniques are also provided for regulating gene expression.

Abstract: Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: Disclosed is an electronic component which includes a removable planar card having a light emitting diode (LED). The electronic component also includes an attachment flange having a first face and a second face substantially parallel to a removable planar card face, and a bushing installed in a hole in the attachment flange. The bushing includes an inner member having a head, a threaded shaft extending from the head. The inner member is inserted through the flange hole such that the head rests on the flange first face. The bushing also includes a sleeve having an threaded inner diameter that is threaded onto the shaft such that the attachment flange is clamped between the inner member and the sleeve and a bottom end of the sleeve is suspended over the LED. Finally, the electronic component includes an optical transmission line inserted into a through hole in the inner member.

Abstract: An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

Abstract: Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An estimation system for deriving multi-dimensional project plans for implementing packaged software applications with self-calibration and refinement of project estimation models, the system includes: a view layer configured to act as a user interface for user inputs and system outputs; a model and control layer configured to implement rules based on a series of estimation and implementation models, and to perform self-calibration and refinement of project estimation models for multi-dimensional project plans; an estimation knowledge base layer configured to hold and derive the series of estimation and implementation models; and wherein the system for self-calibration and refinement of project estimation models for multi-dimensional project plans for implementing packaged software applications is carried out over networks comprising: the Internet, intranets, local area networks (LAN), and wireless local area networks (WLAN).

Abstract: A method (which can be computer implemented) for processing a plurality of adjacent rows of data units, using a plurality of parallel processors, given (i) a predetermined processing order, and (ii) a specified inter-row dependency structure, includes the steps of determining starting times for each individual one of the processors, and maintaining synchronization across the processors, while ensuring that the dependency structure is not violated. Not all the starting times are the same, and a sum of absolute differences between (i) starting times of any given processor, and (ii) that one of the processors having an earliest starting time, is minimized.

Abstract: An apparatus, system, and method are disclosed for web service access to a remote data source procedure. The method includes receiving a web service request from a client and identifying the procedure call identifier within the web service request. The web service request includes a procedure call identifier and zero or more parameters. The method includes creating a procedure call to a data source procedure accessible through an Application Program Interface. The procedure call is created at least in part by ordering parameters of the procedure call based on an order of the zero or more parameters in the web service request. The parameters of the procedure call are ordered without using an explicit parameter mapping. The method includes sending a web service response to the client in response to receiving a response from the data source procedure. The web service response includes information responsive to the procedure call.

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

Abstract: Presents remote servlets collaboration. A method includes: creating a common registry; creating an extended context in response to an external request, wherein the extended context can invoke the resources within the common registry; performing initializing configuration on a plurality of servlets, and registering a plurality of servlets in the common registry, wherein a plurality of servlets being located on different Java virtual machines, or being located in different servlet containers on the same Java virtual machine; and a plurality of servlets collaborate with each other by being invoked through the extended context. It can implement collaboration between servlets located on different virtual machines or even servlets on the same virtual machine but within different servlet containers, because in a converged application service system, not only between HTTP servlets or between SIP servlets but also between HTTP servlets and SIP servlets there is necessity to collaborate.

Abstract: There is disclosed a system and method for identifying a variable type during coding of a software program. In an embodiment, the method comprises defining a unique variable type string for the variable type, and when a unique variable type string is typed adjacent to a new variable name, converting the unique variable type string to a variable type identifier tag attached to the new variable name. Each unique variable type string may be defined as a prefix or a suffix. In another embodiment, the method further comprises defining a unique variable scope string for a variable scope, and when a unique variable scope string is typed adjacent to a new variable name, converting the variable scope to a variable scope identifier tag attached to the new variable name. The variable type identifier tag and the variable scope identifier tag may both be attached to the new variable name in a subscript font and/or superscript font.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: Disclosed are a method, computer program product and apparatus for integrating resource and coordinator components in a heterogeneous computer system. The technique disclosed involves the introduction of a negotiation phase into the resource enlistment or registration process wherein the resource component and coordinator component request and respond with indicators showing the quality of service that each supports, thus jointly establishing at runtime a quality of service to be supported for the resource and coordinator pairing. The qualities of service may include commit phase support and recovery support.