Abstract: Various embodiments of the present invention are generally directed to a method and system for functionally verifying a network device design programmed into a hardware logic verification system. The method and system encapsulates and de-encapsulates test patterns generated by a tester application into and out of network packets, which are further encapsulated into and de-encapsulated from enclosing data packets for fast and efficient delivery to the network device. Such method and system decreases functional verification times for a network device DUT while requiring little to no modification of existing tester applications and functional verification hardware.

Abstract: The present disclosure relates to a method for analog-to-digital converter based decision feedback equalization. The method may include providing an integrated circuit including a SerDes circuitry having a transmit circuitry and a receiver circuitry. The method may further include receiving a high-speed data stream at the receiver circuitry and converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter. The method may also include providing the digital signal to a digital decision feedback equalization circuitry via the successive approximation analog-to-digital converter.

Abstract: The present patent document relates a method and apparatus for compressing probe system data in hardware functional verification systems used to verify user logic designs. Such systems can create large amounts of data every data cycle, which can include many bits that do not toggle from one cycle to the next. Compressing such data is possible by arranging the data in bytes and determining which bytes contain bits that have changed. A status byte may be generated that conveys which bytes contain changed bits. Together the status byte and only the bytes that contain changed bits are transmitted to a host workstation, saving bandwidth on the communication interface.

Abstract: Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Abstract: The present disclosure relates to a method for Analog-to-Digital Converter Based Decision Feedback Equalization. The method may include providing an integrated circuit including a SERDES circuitry having a transmit circuitry and a receiver circuitry and receiving a high-speed data stream at the receiver circuitry. The method may also include converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter and providing the digital signal to a digital decision feedback equalization circuitry via the successive approximation analog-to-digital converter. The method may also include generating an output signal at a phase locked loop and receiving the output signal at a multi-loop clock and data recovery circuitry.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different layout contexts. The method may extract parasitics between components and analyzes impact(s) of layout dependent effect(s) on an electronic design by performing simulation(s) with layout dependent effect(s) in the schematic domain and may perform some partial routing based on some routing style(s) in each of the different layout contexts to generate just enough interconnects that may affect the electronic design.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Abstract: An adjustable gain amplifier system having cleanly adjustable and stable linearized gain is provided for amplifying an input signal. The system generally comprises a main amplifier and a linearized transconductance amplifier coupled thereto, which generates an amplified current signal in response to the input signal according to a variably defined transconductance factor. The linearized transconductance amplifier includes a linearized transconductance portion and a translinear current amplifier portion coupled thereto. The linearized transconductance portion generates an intermediate current signal based upon a voltage of the input signal, and forms an unswitched resistor-based conduction path for that intermediate current signal. The translinear current amplifier portion forms a translinear loop section for amplifying the intermediate current signal to generate the amplified current signal.

Abstract: The present disclosure relates to a computer-implemented method for electronic design visualization. The method may include providing, using at least one computing device, an electronic design and identifying a plurality of power domains associated with the electronic design. The method may further include associating, using the at least one computing device, at least two of the plurality of power domains with a particular group and displaying one or more of the plurality of power domains in a hierarchical manner.

Abstract: Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller and therefore easier to understand and debug.

Abstract: Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.

Abstract: Disclosed is an improved method, system, and computer program product for implementing flexible models to perform efficient prototyping of clock structures in electronic designs, which allows for very efficient analysis of the electronic designs. Some approaches pertain to usage of the flexible abstraction models that also include clock abstractions to more efficiently perform analysis upon the electronic designs. This allows greater analysis efficiency with regards to timing analysis and physical analysis.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.