Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 8863050
    Abstract: In a system, method, and computer program product for analyzing faults in a circuit design, variation of analog fault coverage as a function of bridge resistance values is computed in a single simulation run. A simulator stores intermediate circuit states for each fault resistance value, and performs short interval simulations that may re-use intermediate states as initial solution estimates for simulation of the next fault resistance value. Initial fault resistance values are reduced during simulation passes to aid simulator convergence. The selected evaluation order of test points, faults, and fault resistance values reduces computational and storage costs. Embodiments enable test engineers to rapidly understand if analog defect tests are only sufficient for identifying defects of a certain type and/or value, and to determine fault coverage variability over a full process space.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Victor Zhuk
  • Patent number: 8863052
    Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dhuria, Naresh Kumar, Umesh Gupta, Pradeep Yadav, Prashant Sethia
  • Patent number: 8862439
    Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Kenneth L. McMillan, Shmuel Sagiv
  • Patent number: 8863048
    Abstract: Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design by identifying rules for a first layer and for second layer(s) adjacent to the first layer, determining one or more sets of grids based on the rules, extending or implementing shapes to terminate at some grids of the one or more sets of grids, and populating the data of the ends of the shapes in the first layer in a data structure. The one or more sets of grids are in direction(s) perpendicular to the routing direction(s) of the first layer and have one or more grid pitches determined based at least in part upon routing pitch(es) of the second layer(s) and rule(s) for vias.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vassilios Gerousis, Shuo Zhang, Stefanus Mantik, Yuan Huang, Jing Chen, Jianmin Li
  • Patent number: 8856700
    Abstract: In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: October 7, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yosinori Watanabe, Walter J. Ghijsen, Michael J. Meyer, Michael T. Y. McNamara, David Van Campenhout
  • Patent number: 8850134
    Abstract: A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points, and aligning a plurality of breaking points with a plurality of burst boundary points to provide single access to data located in the system memory.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Brett Murdock
  • Patent number: 8850381
    Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Subramanian Ganesan, Philip Henry Nils Anthony De Buren, Jinny Singh, David Abada
  • Publication number: 20140281730
    Abstract: A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software debugging tool of a step of the operation as a event of interest, collecting data related to that event of interest. A unique identifier is assigned to the collected data. Access to the collected data is enabled for a second user of the software debugging tool.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Nadav CHAZAN, Ynon Cohen, Yonatan Ashkenazi, Nir Paz, Tal Tabakman
  • Publication number: 20140282414
    Abstract: A computer implemented method for debugging of a program may include parsing a code segment of the program, the code segment invoking one or a plurality of execution events during an execution of the program to derive a plurality of questions, each relating to an execution event of said one or a plurality of execution events, based on the parsing of the code segment and on information recorded during the execution of the program. The method may also include selecting one of the questions as a current question. The method may further include presenting in a user interface the current question with one or a plurality of causes related to the current question, and one or a plurality of other questions of said one or a plurality of questions for selection by the user.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Nadav Chazan, Tal Tabakman, Yonatan Ashkenazi
  • Publication number: 20140282415
    Abstract: A computer-implemented method and system for debugging a program is disclosed. The method may include obtaining data on inter-component calls of a call chain of an execution run of the program between segments of Multilanguage software components of the program, the data relating to the identity of the Multilanguage software components in which these segments are included and an order in which the segments are called in the call chain. The method may further include obtaining a user selection relating to one of the segments of the Multilanguage software components that were called in the call chain. The method may also include invoking a debugger designed for debugging the software component of the Multilanguage software components that includes the selected segment and displaying a user interface of that debugger on a display device.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Meir OVADIA, Rodion MELNIKOV
  • Patent number: 8839183
    Abstract: A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pardeep Juneja, Sanjiib Ghosh, Harindranath Parameswaran
  • Patent number: 8838559
    Abstract: A method is provided to evaluate user interaction with a computer user interface (UI) comprising: receiving a property definition that identifies at least one relationship among prescribed string patterns that correspond to one or more UI events; receiving a log file in a computer readable storage device that includes a plurality of respective chunks of information; determining whether the respective chunks of information within the log file includes a respective string pattern that matches at least one of the prescribed string patterns; configuring a processor to produce an indication of whether the property is satisfied based upon the string pattern matching determinations.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 16, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Donald J. O'Riordan
  • Patent number: 8838430
    Abstract: An apparatus and method for detecting memory access violations in simulations is disclosed herein. A detection tool is designed to automatically perform a violation check for each memory read or write operation simulated in a modeled system. The detection tool is capable of handling a modeled system including one or more memories and/or one or more processors.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 16, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tuay-Ling Kathy Lang, Neeti K. Bhatnagar, Jai Bharat Patel Gulabeela, George F. Frazier, Qizhang Chao
  • Patent number: 8832621
    Abstract: A system and method for evaluating a design layout by identifying squish patterns for configurations of shapes in windows defined for anchors in the layout, identifying deltas between edges of elements in the windows and reducing each delta to a single width are described. Identified squish patterns may be compared to known patterns to determine if the squish pattern is a known good or bad pattern. A squish pattern may be represented by a pixel map such that each pixel is a reduced delta in the window and each pixel has a bit representing a layer in a multi-layer layout. A plurality of stored squish patterns may be searched to identify a matching squish pattern, a specific configuration of the squish pattern, or configurations of the squish pattern having deltas within a specified range.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: September 9, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Ya-Chieh Lai
  • Patent number: 8832612
    Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 9, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Prabal Kanti Bhattacharya, Timothy Martin O'Leary
  • Patent number: 8826211
    Abstract: In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 2, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst
  • Publication number: 20140237440
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 21, 2014
    Applicant: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Michael McSherry, David White, Ed Fischer, Bruce Yanagida, Keith Dennison
  • Patent number: 8812286
    Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Bing Zhu, Platon Beletsky
  • Patent number: 8813009
    Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Wangyang Zhang
  • Patent number: 8813004
    Abstract: An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Hao Ji, Joseph M. Swenton