Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Abstract: A system and method are provided for level shifting signals generated by an electronic circuit with selectively controlled frequency response. A first circuit portion defines a primary path for a signal within an upper region of a predefined signal frequency range, and includes a first capacitor unit establishing a voltage level shift for a signal passing therethrough. A second circuit portion selectively defines a secondary path bypassing the primary path for a signal within a lower region of the predefined signal frequency range, and includes a switched capacitive section disposed in parallel across the first capacitor unit to establish a voltage level shift for the signal passing therethrough. A second capacitor unit charges substantially to a predetermined shift voltage in a charging phase and couples to the first capacitor unit during a transfer phase. An attenuation adjust unit adjustably augments a parasitic capacitance of the first or second circuit portion.

Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.

Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.

Abstract: Method of managing workflow failures in a distributed computing environment. A retry value is associated with one or more workflow elements. An element or section of a workflow that does not successfully execute in the distributed computing network is identified. The workflow that does not successfully execute is retried according to a first retry value. The maximum number of times that the first element can be retried is indicated or represented by the first retry value. If one or more workflow elements fail, parent workflows can be retried according to a parent workflow retry value. Elements of the workflow that failed and successfully executed can be retried when the workflow is retried. Execution of workflow elements can also depend upon a condition concerning one or more other elements.

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).

Abstract: The present invention provides for a solution benefiting from providing for a method and system to reduce the impact of read disturbance while providing improved system performance through optimized activities with minimal impact to overhead. The present invention provides for a highly effective early page migration mechanism, prior to a manufacturer's endurance limit and without a forced block migration, to reduce read disturbance associated with traditional NAND-based memory architectures, in part by identifying a block counter value, determining a block threshold value and early migrating one or more pages of data from the original block location upon the satisfaction of certain criteria.

Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed.

Abstract: Disclosed are methods, systems, and articles of manufacture for synchronizing a software verification flow of an application that uses a user interface. Various embodiments comprise implementing a menu item as a widget and identifying an operation associated with the menu item. A synchronizer is further identified or created for the operation and then registered with the operation such that the synchronizer is activated when the operation is invoked during the software verification flow. Once activated, the synchronizer takes over control of the verification flow and prevents the verification flow from proceeding until a criterion is fulfilled. The synchronizer may be reused among different tests, and the same test case may be rerun on different machines with different computing performance and workloads without producing false positives or false negatives.

Abstract: A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.

Abstract: The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize to the first abstraction to access the memory subsystem. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Prior to accessing a memory page, the system will check the flags, copying the contents of the memory in the other abstraction as needed to maintain coherency. The abstractions can operate either synchronously or asynchronously.

Abstract: A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.

Abstract: A method for efficiently processing a design layout is described. In some embodiments, the method receives an original design layout and a modified design layout. The method identifies a change from the original design layout to the modified design layout by comparing the original and modified design layouts. The method of some embodiments then defines a region based on the location of the identified change within the modified design layout. The method performs a design operation (e.g., placing fills) only on the identified region of the modified design layout.

Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

Abstract: Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or coloring routing track(s). Some embodiments route the physical design with coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Multiple-patterning conflicts may be detected based on the coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Some embodiments route with search-and-repair strategy(ies) to improve or resolve conflict(s). Some embodiments color objects upon their creation, and the layout is thus multiple-patterning design rule clean as constructed.

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.