Abstract: The present disclosure relates to a system and method for use with an electronic circuit design. The method may include providing, using at least one processor, an electronic design and modeling the electronic design to obtain a characteristic distribution associated with the electronic design, wherein modeling includes randomly varying one or more parameters associated with the electronic design. The method may further include identifying at least one key parameter from the modeled electronic design and reducing the electronic design only to the at least one key parameter. The method may also include in response to reducing, randomly varying the one or more parameters and re-modeling the reduced electronic design with the randomly varied one or more parameters.

Abstract: Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.

Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.

Abstract: A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.

Abstract: The present embodiments are directed generally to techniques for providing an interactive environment that gives visual feedback and indicators to identify and/or encourage effective sharing of partially used drill sites, all inside a typical etch-edit environment. Such an interactive environment allows designers to effectively leverage and exploit new PCB manufacturing techniques that allow for multi-net use of a single drill hole.

Abstract: A system, method, and computer program product for interactively viewing output log files in an electronic design automation framework. An interactive log file viewer may be configured to identify text objects (such as warnings and error messages) in log files, to render the text objects in a display according to a registered style, and to define responses triggered by user interface interaction with the text objects. Embodiments may read portions of the log files and use plug-ins to identify, render, and respond as configured, according to the text objects found. Callback actions may provide a user more detailed information corresponding to the text object, such as a tool tip or contextual data, and may highlight and select a corresponding design object in a schematic displayed by an integrated electronic design automation application. An arbitration process may select the best callback action for a given log file.

Abstract: Disclosed are techniques for implementing a physical design of an electronic design with design for manufacturing DFM and design specification awareness. These techniques identify one or more design specifications for generating a floorplan or a placement layout of an electronic design. Floorplanning or placement requirements are determined based in part or in whole upon pertinent electrical parasitics. The floorplan or the placement layout is generated at least by inserting a set of blocks based in part or in whole upon the floorplanning or placement requirements.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design environment. Embodiments may include defining, using at least one processor, a grammar object system including one or more of objects, elements, values and relationships. Embodiments may include generating a technology grammar binary representation, based upon, at least in part, the grammar object system and receiving a technology ASCII representation. Embodiments may further include parsing at least one of the technology grammar binary representation and the technology ASCII representation to generate a technology binary representation and providing the technology binary representation to at least one of a graphical user interface or a database.

Abstract: The present disclosure relates to a system and method for electronic design recommendations. Embodiments may include receiving, using at least one processor, an electronic design. Embodiments may further include recognizing one or more circuits within the electronic circuit design. Embodiments may also include identifying one or more user-specific circuit performance preferences. Embodiments may further include generating a first set of one or more placement and routing topology recommendations based upon, at least in part, the one or more user-specific circuit performance preferences. Embodiments may also include receiving a selection of at least one of the placement and routing topology recommendations. Embodiments may further include generating a second set of one or more placement and routing topology recommendations based upon, at least in part, the selected at least one placement and routing topology recommendations.

Abstract: An emulation system comprises a first computing device having a processor configured to generate a synchronization clock signal on receiving a data transfer request. The first computing device further comprises a first non-transitory machine-readable memory buffer storing machine readable binary data. The emulation system further comprises an emulator controller configured to receive the synchronization clock signal from the first computing device. The emulation system further comprises a memory port controller configured to initiate transfer of the machine readable binary data from the first non-transitory machine-readable memory buffer to a non-transitory machine-readable hardware memory, in response to receiving the synchronization clock signal from the emulator controller, during a latency period of the synchronization clock signal.

Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

Abstract: In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to a design technique that can determine an optimal number and placement of ESD cells in a design for an IC. In embodiments, the technique includes determining an effective resistance criteria between a set of candidate ESD cells to the bumps/pads of the IC and finding a minimum set of ESD cells that covers all the bumps/pads. In embodiments, the technique is employed at the early stage of the design of the IC.

Abstract: A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.

Abstract: Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of the package library of the parent cells to retrieve the layer name, layer number, the design resolution, and/or other information such as design rule information of the parent cells hosting the pcells. Based on the layer number, the resolution, and/or other information the pcells can configure for themselves correct layout geometry without any input from a circuit designer.

Abstract: A method including selecting multiple input parameters of a device configuration environment to perform multiple simulations on an electronic device defined by the device configuration environment is provided. The method with multiple values for the multiple input parameters and a value of an output parameter resulting from the multiple simulations, and extracting a distribution of output parameter values and a distribution of input parameter values from a database. The method also includes finding a correlation involving the multiple input parameters and the output parameter based on a target range of the output parameter, and identifying an expected value of the output parameter using a range of values of the multiple input parameters in the correlation involving the multiple input parameters and the output parameter. A system and a nontransitory, computer-readable medium including instructions to perform the above method are also provided.

Abstract: An approach is described for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes. According to some embodiments, the approach includes performance of parasitic analysis for the interface between nets and primitive/macro cell (blocks). Specifically, the approach includes performing parasitic analysis based on actual location information corresponding to overlap/connection between ports within blocks, external net connections to the ports, and internal net (block net) connections to the port. Thus, by determining the actual locations of the connections (as opposed to a presumed location) the parasitic effects associated with the ports and the connections thereof can be calculated.

Abstract: Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.

Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.

Abstract: The present disclosure relates to a system and method for mapping an RTL vector file to an electronic design. Embodiments may include receiving, at one or more computing devices, an electronic design at an electronic design automation application and reading at least one gate-level netlist associated with the electronic design. Embodiments may also include preparing each gate object with different transformations so to match a register-transfer-level name and reading at least one vector object from one or more register-transfer-level vector files. Embodiments may further include attempting to identify at least one match in the gate-level netlist, wherein the at least one match is a match between a register-transfer-level name and a gate name. Embodiments may also include writing a validation file including at least one of mapped information and unmapped information.

Abstract: The present embodiments relate to reconfiguration of a schematic. According to some aspects, embodiments relate to a method in which a schematic of a circuit is displayed on a graphical user interface of a computing device. The schematic can include a plurality of circuit objects, and at least one interconnect connecting the plurality of circuit objects to define a circuit connectivity. The method further includes defining a schematic reference point on the schematic. The method also includes determining a distance of each circuit object of the plurality of circuit objects from the schematic reference point. The method also includes increasing the distance of each circuit object of the plurality of circuit objects from the schematic reference point relative to a respective size of each circuit object, wherein increasing the distance includes multiplying the distance by a scaling factor. The at least one interconnect is reconfigured to maintain circuit connectivity.