Abstract: Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of solutions may be generated with the second discretization scheme and the plurality of inputs.

Abstract: The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed point is reached. The method may also include identifying a non-X node and providing a path of X-diffusion at a property output.

Abstract: The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions. Embodiments may include generating at least one trace pair depicting a scenario where an assumption from a disabled set holds in a first trace but is violated in a second trace. Embodiments may further include identifying at least one signal associated with the first trace and at least one signal associated with the second trace and comparing the at least one signal associated with the first trace and the at least one signal associated with the second trace.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and identifying a partially routed net associated with the electronic design. Embodiments may further include generating a net graph for the partially routed net and selecting a wire associated with the partially routed net. Embodiments may also include determining a missing current needed to satisfy Kirchhoff's Current Law (“KCL”) along a portion of the wire and generating a virtual terminal attached to the selected wire, wherein the virtual terminal is assigned the missing current.

Abstract: Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.

Abstract: Embodiments may include receiving an input block of data having one or more rows wherein each row includes one or more elements. Embodiments may further include adjusting the input block of data to generate a two-dimensional sorted block of data and identifying at least one position within the two-dimensional sorted block of data that cannot contain a median value or a desired Nth sorted value. Embodiments may also include sorting the two-dimensional block of data along one or more columns to obtain one or more candidate elements that contain the median value or the desired Nth sorted value. Embodiments may include discarding at least one non-candidate element to generate one or more remaining elements and rearranging the one or more remaining elements such that a number of diagonal elements form a column. Embodiments may also include iteratively repeating some of the above operations until a desired value is identified.

Abstract: A circuit and method for reducing intersymbol interference due to pre-cursor distortion. A first set of circuit elements located along a first circuit path of a receiver device process an analog input signal of the receiver to form an equalized representation of the input signal. A second set of circuit elements are located along a second circuit path that has lower latency than the first circuit path. The second set of circuit elements form a scaled signal as one of the following: a scaled representation of the input signal, an inverted scaled representation of the input signal, a scaled derivative of the input signal, and an inverted scaled derivative of the input signal. The scaled signal is combined with the equalized representation to cancel out a pre-cursor portion of the equalized representation.

Abstract: Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic instances correspond to the set of layout components. A layout cell or a figure group may be generated for the set of layout components based in part or in whole upon the schematic connectivity information. The original layout may then be transformed into a transformed layout at least by replacing the set of layout components with the generated layout cell or figure group.

Abstract: Disclosed are techniques for implementing legal placement with contextual awareness for an electronic design. These techniques identify one or more hierarchies from one or more groups or one or more instances located at these one or more hierarchies in a layout or floorplan. A plurality of instances including the one or more identified instances may be promoted to an honorary top hierarchy. A layout operation may then be performed on the one or more identified instances based in part or in whole upon a boundary requirement and context information.

Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.

Abstract: The present embodiments relate to methods and apparatuses for detecting a codeword boundary and/or performing codeword error correction for a bitstream comprising scrambled Reed Solomon codewords. In accordance with some aspects, detecting a codeword boundary involves the use of the parity and symbols from a previous window to help in detecting a codeword boundary when the next input bit is received. In accordance with other aspects, parity symbols are more efficiently updated for each successive candidate input bit. In accordance with still further aspects, error correction during codeword boundary detection can be either partially performed or completely bypassed.

Abstract: Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.

Abstract: The present embodiments relate generally to integrated circuit design, and more particularly to techniques that automatically and dynamically create or adjust a highlight set in a graphical user interface for allowing designers to edit layouts in a hierarchical design in a more productive manner. According to certain aspects, in dense designs and/or designs having complete or partial overlapping shapes, embodiments allow for highlighting more than one hierarchy level with tuned parameters that improve the user experience and enhance user work productivity. According to other aspects, embodiments allow for highlighting shapes using colors and/or widths that allow both highlight and shape to be clearly visible and distinguishable.

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

Abstract: An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.

Abstract: A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Abstract: Aspects of the present invention describe a system and method for providing a single integrated simulation interface running in a single host operating system (OS) thread to observe and control multiple, disparate software and hardware components. Control mechanisms of the present invention provide access to each of the modeled components, including the hardware models, the embedded software components modeled on the bare-hardware elements, and the software applications, processes and threads which are themselves running on embedded software.