Abstract: A hierarchical, rule-based, general property visualization and editing system, method, and computer program for circuit designs is provided. A general rules dictionary is created or obtained that determines how the rules will be applied to the circuit design hierarchy. A hierarchical graphical user interface serves both as an entry means for the properties of the design components, and as a visualization means to view the resolved effective value of the property for each component or sub-hierarchy. The visualization means also provides a mechanism to view the rule resolution process so a user can view and understand the effects of all the rules that have an effect on the property and can modify the rules settings to obtain the desired effective property value. A property configuration file is output from the visualization tool and input into the simulator armed with the same general rules dictionary.

Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process.

Abstract: A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.

Abstract: A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim net signal transition; and determining a delay change based upon nominal and noisy victim signal transition arrival times at a victim net receiver output.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: A simulator for a design of an electronic system includes high-level delay models for architecture resources such as ASICs, CPUs, and busses, for example. The delay models of pipelined ASICs compute static pipeline delays which are then implemented by the system simulator. The ASIC delay models are generic, dynamic, incremental and not intrusive.

Abstract: A method and system for solving satisfiability problems is disclosed. In one embodiment, clauses in a satisfiability problem are organized as a chronologically ordered stack. In another embodiment, the activity of each variable in the satisfiability problem is monitored. An activity counter is maintained for each variable and is incremented each time the variable appears in a clause used in generating a conflict clause. In an embodiment, a branching variable is selected from among the variables in the top clause of the stack when the top clause is a conflict clause. In a further embodiment, one or more conflict clauses in the stack are removed when the search tree is abandoned. In a still further embodiment, the value assigned to a branching variable is selected for purposes of having a uniform distribution of positive and negative literals.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.

Abstract: A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layout metrics from the one or more device variables and the one or more weights; and determining the IC design from the one or more device variables and the one or more net lengths. The IC design includes a schematic and a layout. The process can be repeated as needed according to performance criteria that may include circuit performance metrics and layout performance metrics.

Abstract: A multi-faceted portal site acts as a server in the context of an n-tier client/server network, and connects electronic designers and design teams to design and verification tool and service providers on the other through a single portal site. Tools and services accessible to users through the portal site include electronic design automation (EDA) software tools, electronic component information, electronic component databases of parts (or dynamic parts), computing and processing resources, virtual circuit blocks, design expert assistance, and integrated circuit fabrication. Such tools and services may be provided in whole or part by suppliers connected to the portal site. Users accessing the portal site are presented with options in a menu or other convenient format identifying the tools and services available, and are able to more rapidly complete circuit designs by having access to a wide variety of tools and services in a single locale.

Abstract: A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, and an impact is determined of the variations of feature dimensions on electrical characteristics of the integrated circuit. An impact is determined of the topological variations on electrical characteristics of the integrated circuit. An RC extraction tool is used in conjunction with the using of the model and the determining of the impact.

Abstract: The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.

Abstract: An auto-zero circuit is disclosed. The auto-zero circuit includes a first set of circuits for implementing a first auto-zero phase and a second set of circuits for implementing a second auto-zero phase. The first set of circuits includes a first differential amplifier and a first feedback path coupled between an output of the first differential amplifier and an input of the first differential amplifier. The second set of circuits includes a second differential amplifier and a second feedback path coupled between an output of the second differential amplifier and an input of the first differential amplifier, where the second feedback path includes an attenuation capacitor for reducing charge injection error and noise error of the auto-zero circuit and a holding capacitor for holding a voltage to be used to correct charge injection error introduced by the first feedback path.

Abstract: A receiver architecture is disclosed for use in Time-Division Multiple Access (TDMA) and related digital radio applications which combines the principal benefits of the conventional hard-limiting and linear receiver architectures to support switched-antenna diversity and multipath equalisation without the need for receiver gain control. A further feature of the receiver architecture is that minimises the dynamic range needed by the digital signal processing stages thereby reducing complexity, power consumption and cost compared to known arrangements. The (TDMA) radio frequency signal is separated into two components by the analogue section of the receiver: one component characterising the signal's phase, either absolute or differential, the second component characterising the signal's instantaneous magnitude. The (constant-envelope) phase component is digitised by an analogue-to-digital converter (ADC) to form a sequence of phase samples.

Abstract: A method for extracting capacitance from a layout record includes solving a matrix equation to obtain a set of capacitors that account for metal fill while eliminating floaters. A method for extracting capacitance from a layout record includes partitioning floaters into disjoint sets, and converting a capacitance matrix into block-diagonal form by ordering conductors according to the disjoint sets.

Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.

Abstract: Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of specifications, computing a first set of design costs for the first group of specifications, estimating a second set of design costs for the second group of specifications using a predetermined set of reference costs, and determining a design cost of the design point using the first set of design costs and the second set of design costs.