Abstract: A method for encoding elements of an electronic design generates a flattened hierarchy of a parameterized cell of the electronic design, selects common and unique parameters of each element in the parameterized cell, and generates a physical design quantization characteristic value from the selected common and unique parameters.

Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.

Abstract: Embodiments of the present invention provide a virtual-view schematic editor for use in CAD systems. In response to a user request, the editor selects elements from a CAD database, determines the connectivity between the elements, and renders the elements on a single display. Virtual views may be created and stored for later re-use within the system.

Abstract: A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.

Abstract: A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.

Abstract: System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each hierarchical level of the hierarchical netlist in a top-down fashion, and generating the hierarchical netlist using the set of net collections and the set of cross-coupling capacitor collections.

Abstract: A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit.

Abstract: An system and method are disclosed for efficiently approximating analytical circuit device models. A preferred embodiment includes a method for obtaining smooth and accurate approximations of analytical device models, comprising the steps of identifying a first set of measurement units; locating two or more sets of units that neighbor one or more of said measurement units; for each set of the two or more sets of neighbor units, obtaining the union of one or more of said sets of neighbor units and the first set of measurement units; calculating the smoothness of the analytical device model within one or more of said unions; and selecting at least one of said unions within which the analytical device model is the smoothest as the new set of measurement units.

Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Abstract: A system for creating efficient vias between metal layers in semiconductor designs that employ diagonal wiring is disclosed. The system combines advantages of both octagonal shaped vias and square shaped vias. Specifically, octagonal shaped vias are ideal for integrated circuit layouts that contain diagonal wiring since the diagonal wiring may be placed closer to the center the via due to the bevel corners. However, octagonal vias are difficult to manufacture. Square vias have been traditionally used within integrated circuits and the techniques to manufacture square vias are well-known. Since the final manufactured output of an ideal square via is similar to the final output of an ideal octagonal via, one system that may be employed is to design an integrated circuit with octagonal vias and then replace those octagonal shaped vias with square vias just before manufacturing. The replacement square vias must be chose to produce an output shape that is very similar to the output of the ideal octagonal via.

Abstract: The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

Abstract: A hardware emulator having a first primitive for evaluating functions having a first input width and a second primitive, coupled to the first primitive, for evaluating a function having a second input width, where the first input width is unequal to the second input width. The use of either the first primitive or the second primitive is selected depending upon the function to be evaluated.

Abstract: Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a yield of the design using the representative design point and a statistical model of manufacturing process variations, generating statistical corners in accordance with results of the statistical simulation, and optimizing the design in accordance with the statistical corners using an iterative process.

Abstract: A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

Abstract: A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The method further includes arranging the subcircuits from the hierarchically arranged set of branches into one or more groups, determining a data structure for each subcircuit in a group that supports a combination of selectively flattened and selectively expanded group of subcircuits, selecting a subcircuit as a simulation leader and identifying remaining subcircuits as followers in the group, where the simulation leader have states substantially equivalent to the followers, simulating the respective simulation leader of each group using a selectable simulation driver, and replicating simulation results of the respective simulation leader of each group to its followers.

Abstract: Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.

Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.

Abstract: A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.