Abstract: A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive input data are activated, thereby enabling certain resolution devices. The enabled resolution devices are executed using data in the nodes that are connected to the enabled resolution devices. Iterations of executing resolution devices are performed until stable node values are determined.

Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

Abstract: A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has an output operatively coupled to a control terminal of the transistor. The second switch is operated by a second, non-overlapping clock pulse from the clock generator. A current output by the frequency-to-current converter in response to the continuous question of first and second switches is linearly proportional to the frequency of the reference clock and the capacitance of the digitally selectable capacitor.

Abstract: A method for generating lithography marks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract: Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: Some embodiments of the invention provide a method for costing an expansion to a two-dimensional state in a path search that searches for a path between two sets of states in a space. The method identifies a cost function that is defined over the two-dimensional state. The method computes a second cost function that is defined over the two-dimensional state. It also computes a third cost function that is defined over the two-dimensional state. It then adds the second and third cost functions to obtain the first cost function.

Abstract: An open system for multiple discrete, geographically disperse simulation engines to communicate with each other across a distributed electronic network, such as the Internet, comprises a portal accessible to the simulation engines over the network. Local portions of the simulation may be run separately by each simulation engine, and the output data files are stored on and managed by the portal. A co-simulating engine may request an output data file stored by the portal and use that data as input for its downstream portion of the simulation. In this fashion, multiple geographically disperse simulation engines can test bench their designs in an open, network centric simulation environment.

Abstract: Responding to a single command, a layout versus schematic (LVS) tool processes layout data describing positions of conductors on layers of an IC to produce data representing a shape recognition layer depicting boundary shapes of spirals of drawn inductors. The boundary shape of a spiral is the shape of the spiral as viewed from above with all of the layers of conductive material forming the spiral superimposed. The LVS tool then processes the shape recognition layer data to identify the type and position of each drawn inductor, to determine whether each inductor's spiral turns are of uniform width and spacing, to detect connectivity violations, and to determine parameters relating to the shape of the spiral from which its inductance can be computed.

Abstract: A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.

Abstract: Some embodiments of the invention provide novel methods for representing items in a design layout. For instance, they use a method that identifies several half-planes, that when intersected, define the shape of the item. Some embodiments use a method that (1) identifies a first set of location data for the item with respect to a first coordinate system, (2) identifies a second set of location data for the item with respect to a second coordinate system, and (3) specifies the item in terms of the first and second set of location data. In some embodiments, both the first and second coordinate systems have first and second coordinate axes. Some embodiments use a method that receives a first set of data that defines the item with respect to a first coordinate system of the design layout.

Abstract: A method of synthesis of a model representing a design of an integrated circuit is provided including associating a test environment with a first model representing a design of an integrated circuit; translating the first model of the design to a second model of the design; and automatically generating an adaptor that adapts the second model to the test environment.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract: A pertubative approach based on the Born approximation resolves weakly nonlinear circuit models without requiring explicit high-order device derivatives. Convergence properties and the relation to Volterra series are discussed. According to the disclosed methods, second and third order intermodulation products (IM2, IM3) and intercept points (IP2, IP3) can be calculated by second and third order Born approximations under weakly nonlinear conditions. A diagrammatic representation of nonlinear interactions is presented. Using this diagrammatic technique, both Volterra series and Born approximations can be constructed in a systematic way. The method is generalized to calculate other high-order nonlinear effects such as IMn (nth order intermodulation product) and IPn (nth order intermodulation intercept point). In general, the equations are developed in harmonic form and can be implemented in both time and frequency domains for analog and RF circuits.

Abstract: Disclosed are novel methods and apparatus for transforming sequential logic designs into equivalent combinational logic. In an embodiment of the present invention, a design method for transforming sequential logic designs into equivalent combinational logic is disclosed. The design method includes: simulating each stage of a clocking sequence to produce simulation values; saving the simulation values; and performing a plurality of backward logic traces based on the saved simulation values to provide an equivalent combinational logic representation of a sequential logic design.

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

Abstract: In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.