Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generated by connecting a second plurality of M capacitors in a second plurality of M+1 configurations. The first plurality of N capacitors and the second plurality of M capacitors have one or more capacitors in common. The integers M and N may be equal, although this is not required. The first plurality of configurations is different than the second plurality of configurations, thereby providing different multiplication factors for the first and second pluralities of configurations. In one embodiment, the first plurality of (N+1) configurations results in an output voltage of about ¾× an input voltage.

Abstract: A charge pump provides a multiplication factor of ? by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the output terminal is connected to the common node of the first and second capacitors. In a third mode, the voltage potential across the second capacitor is subtracted from the sum of the input voltage and the voltage potential across the first capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired ?× voltage multiplication. This relatively low multiplication factor can be beneficial in applications requiring 2.5V and 1.8V supplies for integrated circuits, particularly where the input voltage is provided by a lithium battery.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor. During programming, the reference NVM transistor has a floating gate coupled to ground through a first set of capacitors, and coupled to a reference voltage through a second set of capacitors. The program threshold voltage of the first NVM transistor is dependent on the first and second sets of capacitors. The first and reference NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Capacitors can be transferred between the first set and the second set, thereby providing precise adjustment of the single ended reference voltage.

Abstract: A charge pump provides a multiplication factor of 4/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the voltage potential across the first capacitor is added to the input voltage to generate the output voltage. In a third mode, the voltage potential across the first capacitor is subtracted from the sum of the input voltage and the voltage potential across the second capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 4/3× voltage multiplication. This relatively low multiplication factor can be beneficial in applications such as white LED driver circuits, particularly where the input voltage is provided by a battery.

Abstract: A charge pump provides a multiplication factor of 4/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the voltage potential across the first capacitor is added to the input voltage to generate the output voltage. In a third mode, the voltage potential across the first capacitor is subtracted from the sum of the input voltage and the voltage potential across the second capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 4/3× voltage multiplication. This relatively low multiplication factor can be beneficial in applications such as white LED driver circuits, particularly where the input voltage is provided by a battery.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor, wherein a first voltage is applied to the control gate of the first NVM transistor, and a reference voltage is applied to the control gate of the reference NVM transistor. The threshold voltage of a second NVM transistor is programmed while coupled in parallel with the reference NVM transistor, wherein a second voltage is applied to the control gate of the second NVM transistor, and the reference voltage is applied to the control gate of the reference NVM transistor. The first and second NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltages of the first and second NVM transistors.

Abstract: A step down switching regulator circuit that is particularly well-suited to drive high power LEDs includes a crossover conduction mode (XCM) control circuit that maintains operation at the crossover point between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). This XCM operation provides an inductor current waveform that ramps up and down between zero and a desired maximum current. One or more comparators in the XCM control circuit can be used to control switching between the inductor current ramp up and ramp down phases. In this manner, complex feedback loop logic and PID controlled PWM signal generation logic can be avoided, and the need for external sense resistors and associated interface pins can be eliminated.

Abstract: A digital potentiometer includes a string of impedance units in series. The string includes identical first and second sets of impedance units whose individual impedance values increment by a power of two. One of a plurality of switches is coupled in parallel with each respective impedance unit. The switches that are coupled to the first set of impedance units receive logical control signals complementary to logical control signals received by the respective switches coupled to the second set of impedance units, so that for every impedance unit of the first set that is bypassed (not bypassed), the identical impedance unit of the second set is not bypassed (bypassed). The string may include only the first and second sets of impedance units, or may include at least one third impedance unit in series with the first and second sets in a multi-stage design.

Abstract: Embodiments of a digital potentiometer are disclosed that require lesser numbers of components than conventional digital potentiometers. A first string of elemental impedance devices, and at least one bulk impedance device, are provided between first and second reference terminals. The first string of elemental impedance devices is tapped by wiper switches. The at least one bulk impedance device has an impedance greater than an impedance of the first string. If desired, second and third bypassable impedance device strings also may be provided between the first and second reference terminals, with the impedance of the respective second and third strings being between the impedance of the first string and the impedance of one bulk impedance device. One or more dummy structures each including an impedance device in parallel with a permanently-on switch also may be between the first and second reference terminals to improve linearity.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices are each connected to a respective one of the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal. The configurable output stage includes a buffer and a second switching device. The second switching device is operable to bypass the buffer. A switching circuit controls switching of the first switching devices. The switching circuit includes a Gray-code counter, a Gray-code decoder, and a make-before-break circuit that controls the timing of the switching of the wiper switches.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A digital potentiometer includes a string of impedance units in series. The string includes identical first and second sets of impedance units whose individual impedance values increment by a power of two. One of a plurality of switches is coupled in parallel with each respective impedance unit. The switches that are coupled to the first set of impedance units receive logical control signals complementary to logical control signals received by the respective switches coupled to the second set of impedance units, so that for every impedance unit of the first set that is bypassed (not bypassed), the identical impedance unit of the second set is not bypassed (bypassed). The string may include only the first and second sets of impedance units, or may include at least one third impedance unit in series with the first and second sets in a multi-stage design.

Abstract: A voltage reference circuit includes storage, programming, and test floating gate transistors. The floating gates of the storage and programming transistors are shorted, while the floating and control gates of the test transistor are shorted. The test and storage transistors are connected between an input terminal and the inputs of a comparator, with the control gate of the test transistor also being connected to the input terminal. A reference voltage is programmed by applying the reference voltage to the input terminal and increasing the net positive charge on the floating gate of the storage transistor (via the programming transistor) until its source voltage matches the source voltage of the test transistor. Then, any test voltage at the input terminal can be compared to the programmed reference voltage by comparing the source voltages of the test and storage transistors.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a reference NVM transistor, wherein a first voltage is applied to the control gate of the first NVM transistor, and a reference voltage is applied to the control gate of the reference NVM transistor. The threshold voltage of a second NVM transistor is programmed while coupled in parallel with the reference NVM transistor, wherein a second voltage is applied to the control gate of the second NVM transistor, and the reference voltage is applied to the control gate of the reference NVM transistor. The first and second NVM transistors are then coupled in parallel, and a differential amplifier is used to generate a single-ended reference voltage in response to the programmed threshold voltages of the first and second NVM transistors.

Abstract: A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any control input from off-chip components or signals. Therefore, the space requirements for LED circuits that make use of the LED driver IC can be minimized. Also, the non-volatile memory storage of settings data eliminates the need for an initialization or configuration input each time the LED driver IC is powered on. The non-volatile memory can be a one-time programmable memory or can be a reprogrammable memory.