Abstract: Circuitry for programming a non-volatile memory of an integrated circuit is disclosed. The circuitry requires only three pins: a power pin, a ground pin, and a data pin. Programming mode is initiated by coincidentally applying high voltages at the power pin and the data pin. The memory cells may be programmed individually in sequence, or all at once. A clock signal for selecting the memory cells is obtained through serial high voltage pulses applied to the power pin. The clock signal increments a state machine, which in turn causes one or more of the memory cells to be selected. Binary data is provided to the data pin, is stored, and is then provided to the memory cells. A high voltage pulse subsequently received at the data pin is passed to the memory cells, and causes the stored data to be programmed into the selected memory cell(s).

Abstract: A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any control input from off-chip components or signals. Therefore, the space requirements for LED circuits that make use of the LED driver IC can be minimized. Also, the non-volatile memory storage of settings data eliminates the need for an initialization or configuration input each time the LED driver IC is powered on. The non-volatile memory can be a one-time programmable memory or can be a reprogrammable memory.

Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.

Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.

Abstract: A low dropout voltage regulator circuit with non-Miller frequency compensation is provided. The circuit includes an input voltage terminal; an output voltage terminal; an error amplifier having a first input coupled to a reference voltage; a voltage follower coupled to an output of the error amplifier; a pass device; and a feedback network. An input terminal of the pass device is coupled to the input voltage terminal. A control terminal of the pass device is coupled to an output of the voltage follower. An output terminal of the pass device is the output voltage terminal. The feedback network includes two resistors in series between the output voltage terminal and ground. A node between the resistors is coupled to a second input of the error amplifier. A frequency compensation capacitor also is coupled between the output voltage terminal and the node.

Abstract: A low dropout voltage regulator with non-Miller frequency compensation is provided. The LDO circuit has two wide-band, low-power cascaded operational transconductance amplifiers (OTAs): an error amplifier and a unity-gain-configured voltage follower. The unity-gain-configured voltage follower drives a gate of a power PMOS path transistor with a high parasitic gate capacitance. The wide-band, low-power OTAs enable the use of a single, low-value load capacitor with a low equivalent series resistance (ESR). A frequency compensation capacitor is connected in parallel with the upper resistor of a feedback network, which introduces a zero-pole pair that enhances the phase margin close to unity-loop-gain frequency.

Abstract: A method for supervising the execution of a job in a license restricted environment is disclosed. According to the license restricted environment, some networked machines are licensed for a first type of processing and other machines are licensed for a second (or other) types of processing. In executing a job that requires processing portions or segments of both the first and second types of processing, when the job begins processing the job using the first types of processing on a suitably licensed machine and then fails when attempting to process the job using the second types of processing on the same machine because of a license violation. The method for supervising operates in an automated fashion to detect the stoppage of the job due to license failure and to resume the remaining portions or segments of the job for processing using the second types of processing on a suitably licensed machine.

Abstract: An electrically alterable semiconductor memory device having an array of memory cells formed by individual transistors. The structure of the memory cells is compact and facilitates high density memory devices and is particularly well suited for contactless, virtual ground arrays. The memory cells can be read and programmed a page at a time. The memory cells can also be programmed using source-side hot-electron injection with improved efficiency and lowered programming currents.

Abstract: A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of self-aligned memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation.

Abstract: A semiconductor memory device that operates as a normal memory device as long as existing memory is being addressed, but appears to external hardware and software to have a larger size (or standard size) memory array than is actually present in the semiconductor memory device is disclosed. To external hardware and software, the semiconductor memory device operates as if it has more addressable memory cells than in fact actually exist in the memory array. When addressing missing memory cells, the semiconductor memory device emulates or mimics their presence for the benefit of the external hardware or software. Preferably, the semiconductor memory device is a non-volatile electrically alterable semiconductor memory device. A method for emulating missing memory cells is also disclosed.

Abstract: A charge stacking, high voltage generating circuit is provided wherein a plurality of capacitors are charged in parallel and discharged in series through a single diode to an output terminal. A switching circuit is used to connect each of the capacitors in parallel between a first supply voltage and a second supply voltage during a first half clock cycle. This configuration allows the capacitors to charge during this first half clock cycle. During a second half clock cycle, the switching circuit connects the charged capacitors in series between the first supply voltage and the output terminal through a single diode. The series configuration of the capacitors is such that the voltage at the output terminal is approximately equal to the first supply voltage, plus the sum of the voltages of the charged capacitors, minus the threshold voltage drop across the series diode.

Abstract: A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.

Abstract: A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each other. The plurality of pump units are switched at different times during the pump frequency to minimize noise generation. In one embodiment, the charge pump circuit is capable of delivering 8 mA of current.

Abstract: Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.

Abstract: An array of floating gate transistors is connected so that some of the floating gate transistors within the array can be erased without affecting the state of other floating gate transistors within the array, or in the alternative, the entire array of floating gate transistors can be erased simultaneously.

Abstract: A circuit senses the state of an EPROM cell transistor and drives an output lead in response thereto. The circuit comprises first and second sense amplifiers, each having inverting and noninverting input leads. The circuit also comprises a reference voltage lead coupled to the inverting lead of the first sense amplifier and the noninverting lead of the second sense amplifier. An EPROM cell transistor is connected to the noninverting lead of the first sense amplifier and the inverting lead of the second sense amplifier. The first sense amplifier is coupled to a first portion of a buffer circuit which couples the output lead to a VCC supply lead, while the second sense amplifier drives a second portion of a buffer circuit which coupled the output lead to ground.

Abstract: Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

Abstract: A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.

Abstract: Disclosed is a rectifier circuit which utilizes field effect transistors, and which includes current sensing resistors to adjust the drive to the field effect transistors to avoid forward biasing the intrinsic bipolar transistor in the field effect transistors to thereby avoid injecting current into the substrate where the field effect transistors are formed on a common substrate. In addition, the current sensing resistors provide a fast startup, which is achieved both in the case where the field effect transistors are formed on a common substrate as well as those implementations where the field effect transistors do not share a common substrate. Current limiting resistors are also included to prevent overloading the field effect transistors and injecting current into the substrate when the field effect transistors share a common substrate.