Abstract: A semiconductor structure includes a plurality of metal layers and a substrate. The plurality of metal layers are provided with a plurality of virtual metal blocks and at least one signal line. A first projection of a first virtual metal block on the substrate is a polygon, the first projection has a plurality of effective sides opposite to a second projection of a target signal line on the substrate, and differences from the plurality of effective sides of the first projection to a straight line where the second projection is located are different, and the first virtual metal block is a virtual metal block, closest to the target signal line, on the target metal layer, and the target metal layer is a metal layer where the target signal line is located.

Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of laminated structures arranged at intervals on the substrate, the laminated structure includes a first conductive layer, an insulating layer, and a second conductive layer, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the laminated structures, and a dielectric layer covering the channel layer; and forming word lines (WLs) extending along a first direction, the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

Abstract: A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.

Abstract: The present disclosure provides a semiconductor device and its preparation method, wherein the preparation method includes providing a substrate, forming bit line units, capacitor contacts and a conductive layer on the substrate, patterning the conductive layer on the substrate by step-by-step etching, etching first grooves to form first conductive parts positioned above the bit line units, protecting sidewalls of the first grooves, and then etching second grooves to form second conductive parts covering sidewalls of the bit line units and third conductive parts covering the capacitor contacts.

Abstract: Embodiments of the present disclosure provide a method and a device for determining a fabrication chamber. According to a current radio frequency power time of each of the fabrication chambers corresponding to adjacent process steps and service phases divided based on a service period of the fabrication chambers, a service phase is determined for the current radio frequency power time of each of the fabrication chambers. For target objects processed by the fabrication chambers in the current process step, fabrication chambers for the target objects to enter in a next process step are directly determined according to the service phase of the current radio frequency power time of each of the fabrication chambers.

Abstract: A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Abstract: A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.

Abstract: The present disclosure relates to a package substrate comprising: a substrate having opposing first surface and second surface; at least one vent hole extending through the first surface and the second surface of the substrate, the vent hole comprising at least a long-strip hole.

Abstract: A method for grinding the wafer includes: an initial wafer of which an edge has a test address is provided; a recombined water of which the test address is located in the middle is formed; a following circulation step is performed: a protective layer at least located above the test address is formed on an existing layer of the recombined water; the uncovered existing layer is grinded; the protective layer and the existing layer which is remaining are removed. It is determined whether the test address is exposed, if not, the next circulation step is performed.

Abstract: A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.

Abstract: A simulation method, apparatus, and a storage medium are provided. The simulation method includes: obtaining a pre-built local simulation model of a capacitor array region, wherein the local simulation model is configured to represent first simulation parameters of the capacitor array region; creating a local parameter netlist of a non-capacitor array region, wherein the local parameter netlist includes second simulation parameters of the non-capacitor array region; creating an overall parameter netlist of a peripheral region based on the local simulation model and the local parameter netlist, wherein the overall parameter netlist represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters; and performing simulation on the peripheral region based on the overall parameter netlist.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: A One Time Programmable (OTP) memory can have a memory cell, which includes two series diodes as a fuse structure.

Abstract: The present invention relates to a semiconductor electrostatic protection device, including: a substrate, a deep well region of a first conductivity type being formed in the substrate; a first diode, an anode of the first diode being connected to a first voltage, and a cathode of the first diode being connected to an input/output terminal; and a second diode, an anode of the second diode being connected to the input/output terminal, and a cathode of the second diode being connected to a second voltage; the first diode and the second diode being located in the deep well region of the first conductivity type.

Abstract: An overhead buffer double-entry detection system, which includes an overhead hoist transport, a first sensing unit for scanning and generating detection data of a horizontal range, a driving device for moving the first sensing unit in a vertical range, a controlling unit, and an overhead hoist transport controlling system for sending a detection instruction and a driving instruction to the controlling unit when the overhead hoist transport moves to a corresponding overhead buffer position, whereby the controlling unit bases on the driving instruction to control the driving device to move the first sensing unit in a vertical range, bases on the detection instruction to control the first sensing unit to scan and generate detection data of each horizontal range within the overhead buffer during movement process, and bases on the detection data of each horizontal range within the overhead buffer to judge whether there is obstacle in the overhead buffer.

Abstract: Some of the embodiments of the present application provide a semiconductor structure and a method of manufacturing the same, the method of manufacturing the semiconductor structure comprising: providing a base; performing a first electroplating process to form a first electroplated layer on the base; performing a second electroplating process to form a second electroplated layer on the surface of the first electroplated layer, the current density of the second electroplated layer being greater than the current density of the first electroplated layer.

Abstract: Provided is a method of high-density pattern forming, which includes: providing a substrate; forming a hard mask layer on the substrate; forming a sacrificial layer on the hard mask layer; forming photoresists arranged at intervals on the sacrificial layer; etching the sacrificial layer to enable the sacrificial layer to form a mandrel corresponding to the photoresist one by one, wherein a cross-sectional size of the mandrel gradually decreases from an end of the mandrel away from the hard mask layer to an end close to the hard mask layer; forming an isolation layer on the mandrel; removing the isolation layer on the top of the mandrel, the isolation layer covering the hard mask layer, and the mandrel to form an isolation sidewall pattern; and transferring the isolation sidewall pattern to the hard mask layer.

Abstract: A method for forming the packaging structure includes: providing a substrate; forming a plurality of mutually independent conductive wires on the substrate, wherein a trench is provided between adjacent conductive wires; oxidizing side walls of each of the conductive wires to form a barrier layer; and forming a solder mask at least filling the trench.

Abstract: The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.