Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Publication number: 20230010642
    Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, at least a gate structure, a first dielectric layer covering a surface of the substrate and the gate structure being formed on the substrate, and a first dielectric layer on a side surface of the gate structure serving as a first sidewall; forming a sacrificial sidewall on a side surface of the first sidewall; removing the sacrificial sidewall after a first doped region and a second doped region are respectively formed in the substrate on both sides of the sacrificial sidewall; forming a second sidewall on a side surface of the first sidewall.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yi TANG
  • Publication number: 20230011266
    Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided, and the substrate includes an active surface and a back surface opposite to the active surface. An etching stop layer is formed on the back surface of the substrate. The substrate is fixed onto a first temporary carrier to make the etching stop layer be located between the substrate and the first temporary carrier. The substrate is etched until reaching the etching stop layer to form a via structure penetrating through the substrate.
    Type: Application
    Filed: February 17, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230012005
    Abstract: A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.
    Type: Application
    Filed: December 8, 2021
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: You LV
  • Publication number: 20230009877
    Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huan LU
  • Publication number: 20230011180
    Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng YANG, Yi Tang
  • Publication number: 20230009525
    Abstract: A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn HUANG
  • Publication number: 20230010386
    Abstract: An input sampling method includes the following: acquiring a first pulse signal and a second pulse signal respectively; widening a pulse width of the first pulse signal to obtain a widened first pulse signal; shielding an invalid signal in the second pulse signal based on the widened first pulse signal to obtain a to-be-sampled signal; and finally, sampling the to-be-sampled signal based on a clock signal. In this way, prior to signal sampling, the invalid signal is shielded to avoid additional power consumption caused by sampling the invalid signal, and at the same time, the pulse width of the signal is widened to avoid sampling failure.
    Type: Application
    Filed: March 31, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn HUANG
  • Publication number: 20230008332
    Abstract: A parsing method includes the following: during parsing target bank, performing a row hammer operation on a logical row in target bank to determine a physical position relationship of the logical row; repeatedly performing the operation of performing the row hammer operation on the logical row in target bank to determine the physical position relationship of the logical row until all logical rows have been parsed; and determining a mapping relationship used for recording physical position relationships of multiple logical rows according to a linked list; where performing the row hammer operation on the logical row in target bank includes: acquiring a to-be-parsed logical row in target bank including multiple logical rows; performing the row hammer operation on the to-be-parsed logical row until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaolei LI, Baolei HAN
  • Publication number: 20230009103
    Abstract: A method for forming a semiconductor device includes the following: after sacrificial side walls are formed on the side walls of conductive connection structures, forming an outer side wall material layer on the surfaces of the sacrificial side walls; perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls; removing the sacrificial side walls through the pinholes to form air gaps; and forming a cover layer for sealing the pinholes.
    Type: Application
    Filed: February 12, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: DAEJOONG WON
  • Publication number: 20230008364
    Abstract: A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.
    Type: Application
    Filed: March 30, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian XU
  • Patent number: 11550350
    Abstract: A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 10, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Lei Zhu, Zhiyong Chen, Jinlai Luo
  • Patent number: 11552832
    Abstract: Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: January 10, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jianfei Hu
  • Patent number: 11552092
    Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: January 10, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kui Zhang
  • Publication number: 20230005516
    Abstract: A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.
    Type: Application
    Filed: February 17, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn HUANG
  • Publication number: 20230005869
    Abstract: A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.
    Type: Application
    Filed: February 12, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zengyan FAN
  • Publication number: 20230005919
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Deyuan XIAO, Yi JIANG, Guangsu SHAO, Xingsong SU, Yunsong QIU
  • Publication number: 20230005920
    Abstract: The semiconductor structure includes a first capacitive structure located on a substrate and first support columns. A plurality of first support columns are disposed on the substrate in parallel and spaced apart from each other, and are located in a same plane parallel to the substrate. The first capacitive structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The semiconductor structure further includes a plurality of first segmentation trenches. The first segmentation trenches divide the first capacitive structure into a plurality of capacitors. A first insulation layer is disposed between the corresponding first lower electrode layers of the adjacent capacitors. The corresponding first upper electrode layers of the adjacent capacitors are electrically connected to each other.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES,INC.
    Inventors: Guangsu SHAO, Deyuan XIAO
  • Publication number: 20230005810
    Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Luguang WANG, Xiaoling WANG
  • Publication number: 20230005559
    Abstract: A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn HUANG
  • Publication number: 20230005867
    Abstract: A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.
    Type: Application
    Filed: February 11, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi CHUANG