Abstract: Systems and methods for tracking a sports object are provided. A sports object includes a core assembly arranged within a shell and having multiple components to receive and transmit signals corresponding to movement of the sports object, as well as to support operational tracking of the sports object. The core assembly includes a multi-layer printed circuit board (PCB) comprised of a plurality of sections. The PCB is configured to at least partially envelope the energy storage device at a geometric center of the assembly. The PCB is connected to one or more antennas (e.g., via one or more contacts), which may be arranged on one or more sections of the PCB, arranged on a surface of the shell, and/or in a volume within the shell.

Abstract: A real-time tracking system for sports scoring objects and associated methods of use are disclosed. In at least one embodiment, the scoring object provides an at least one object location sensor, an at least one object motion sensor, an object communication device, and a microcontroller. Upon a user desiring to track the at least one scoring object, the system is configured for allowing the object communication device of the scoring object to be placed in communication with a user device. A start location of the scoring object is determined prior to being put into motion. Upon determining that the scoring object is in motion, an at least one motion attribute of the scoring object, as captured by the object motion sensor of the scoring object, is monitored. Upon subsequently determining that the scoring object has come to rest, an end location of the scoring object is determined.

Abstract: An encapsulated electronic device includes a magnetically permeable core structure which is exposed within and coplanar with a flat top surface of the device. A bottom surface of the core may be exposed within the bottom surface of the device. The bottom core surface may be recessed beneath, coplanar with, or protruding from the bottom surface of the device. Alternatively the bottom surface may be encapsulated within the device. A method for manufacturing the exposed core package includes positioning a first component relative to a second component before encapsulating the device. An improved planar magnetic core structure includes internal bevels having a radius greater than or equal to 15% and preferably 25%, 35%, or as much as 50% of the core thickness to reduce concentration of the magnetic field around the internal corners.

Abstract: An optical wavelength dispersion device includes a first substrate, an input unit formed on the first substrate having a slit for receiving an optical signal, a grating formed on the first substrate for producing a first light beam form the optical signal for outputting, and a second substrate covered on the top of the input unit and the grating, wherein the input unit and the grating are formed from a photo-resist layer by high energy light source exposure.

Abstract: An optical wavelength dispersion device includes a first substrate; an input unit formed on the first substrate having a slit for receiving an optical signal; a grating formed on the first substrate for producing a first light beam form the optical signal for outputting; and a second substrate covered on the top of the input unit and the grating; wherein the input unit and the grating are formed from a photo-resist layer by high energy light source exposure.

Abstract: Provided is a method for running cache invalidation in a computer system including: checking whether or not the cache invalidation is in a range mode when the cache invalidation is started; resetting an internal count associated with the invalidation if the cache invalidation is in the range mode; accessing a cache entry; checking whether or not a tag is ‘hit’ as a result of the accessing to the cache entry; checking whether or not a state of the cache is dirty if the tag is ‘hit’; performing write operation on the memory and clearing the cache entry if the state of the cache is dirty; clearing the cache entry if the state of the cache is not dirty; incrementing the internal count by 1 if the tag is not ‘hit’ or if the cache entry is cleared; and ending the cache invalidation if the internal count exceeds a predetermined offset.

Abstract: Provided is a method of decoding instructions in a microprocessor, including: checking existence of instructions when instruction decoding is stared; folding two instructions when two instructions exist; and decoding folded instructions. Accordingly, it is possible to improve performance in a microprocessor by generating one instruction by folding two instructions into one instruction in an instruction decoding period.

Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.

Abstract: A method and apparatus for efficiently converting power from an AC line is disclosed. The power converter supplies power to the load, performing power factor correction at nominal and high loads, i.e. above a predetermined output power threshold, and operating in an on-demand burst mode synchronized to the AC line at low loads, i.e. below a predetermined output power threshold. The duration of an operating interval during which power conversion takes place may be reduced and varied at low loads as a function of the output power demands to increase overall conversion efficiency. The operating interval may be centered about a peak in the input voltage waveshape for operating intervals that are less than a full rectification period. For operating intervals that are less than a full rectification period a modified power factor correction may be used, in which the input current waveshape approximates the input voltage waveshape during the operating interval.

Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.

Abstract: A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A distribution network, comprises: circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal.

Abstract: A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the current source as a function of the outputs and a reference voltage.

Abstract: Disclosed is a method of operating an immediate value in an extendable instruction set computer (EISC) processor, comprising: checking whether or not an unsigned immediate value is used to generate an extension register (ER) value for operating an immediate value; and generating the ER value by performing zero extension for the unsigned immediate value using an unsigned load extension register with immediate (ULERI) instruction if the unsigned immediate value is used. It is possible to improve operational efficiency by preventing an LERI instruction from being unnecessarily executed when an immediate value is operated using a 16-bit instruction in the EISC processor.

Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using one or more serially-connected first stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the first stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.

Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.