Abstract: Environmentally safe, e.g. biodegradable, paint stripper compositions comprising 10-99 parts dimethyl esters of C4-C6 aliphatic dibasic acids, 0.1-40 parts polyvinyl butyral and 1-90 parts water. The compositions can be mixed, e.g. in high shear to provide stable emulsions which strip paint, e.g. varnish from wood. Certain embodiments of the invention also comprise water soluble organic solvents, water-miscible organic solvents, surfactants, emulsifiers, thickeners and/or pigments.

Abstract: A staged method of forming vinyl (e.g.

Abstract: Environmentally safe, e.g. biodegradable, paint stripper compositions comprising 10-99 parts dimethyl esters of C4-C6 aliphatic dibasic acids, 0.1-40 parts polyvinyl butyral and 1-90 parts water. The compositions can be mixed, e.g. in high shear to provide stable emulsions which strip paint, e.g. varnish from wood. Certain embodiments of the invention also comprise water soluble organic solvents, water-miscible organic solvents, surfactants, emulsifiers, thickeners and/or pigments.

Abstract: A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This apparatus reduces, or preferably eliminates, the requirements for application housekeeping, such as garbage collection, by providing substantially more deterministic dynamic memory management operations. Housekeeping, or garbage collection, such as memory compaction and unused space retrieval, are reduced or eliminated. When housekeeping is eliminated, all dynamic memory invocations become substantially deterministic. The invention maps all or a part of a large, sparsely populated logical memory address space used to store dynamically allocated objects, to a smaller, denser physical memory address space.

Abstract: A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object manager for managing the memory objects used by the host processor. The object manager may further comprise an address translation table for translating virtual space addresses for memory objects received from the host processor to physical space addresses for memory elements, and a management table for storing data associated with the memory objects used by the host processor.

Abstract: A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input signal from the second rail of the dual rail driver. In one embodiment, the input signal from the first rail of the dual rail driver can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0.18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from GROUND to 400 MV.

Abstract: A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the search client for generating a matching signal; and a associative memory element coupled to the caching associative element configured to search for data not stored in the caching associative memory element. The search client issues a search request for data to associative cache element. If the matching data is found there, then such matching data is returned to the search client. Alternatively, if the data is not found, then the search request is issued to the main associative memory. The least frequently used data or the least recently used data in the associative memory cache are replaced with the matching data and the higher priority data.

Abstract: An improved wavelength division multiplexing device is disclosed. The improved wavelength division multiplexing device has a diffraction grating for combining a plurality of monochromatic optical beams into a multiplexed, polychromatic optical beam. The improvement in the improved wavelength division multiplexing device is the use of a polymer collimating/focusing lens for collimating the plurality of monochromatic optical beams traveling along a first direction to the diffraction grating, and for focusing the multiplexed, polychromatic optical beam traveling along a second direction from the diffraction grating, wherein the second direction being substantially opposite the first direction.

Abstract: A wavelength division multiplexing device is disclosed. In a preferred embodiment, the wavelength division multiplexing device comprises a diffractive optic collimating lens for collimating a plurality of monochromatic optical beams, a diffraction grating for combining the plurality of collimated, monochromatic optical beams into a multiplexed, polychromatic optical beam, and a diffractive optic focusing lens for focusing the multiplexed, polychromatic optical beam.

Abstract: A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Abstract: A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell stnictuire may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Abstract: A wavelength division multiplexer/demultiplexer is provided that integrates axial gradient refractive index elements with a diffraction grating to provide efficient coupling from a plurality of input optical sources (each delivering a single wavelength to the device) which are multiplexed to a single polychromatic beam for output to a single output optical source.

Abstract: An apparatus for preparing a cooked food product such as a potato chip without the use of oil. The apparatus includes a first infrared heating source to warm the exterior of the sliced potato pieces, a microwave energy source to warm the interior of the potato pieces, and a second infrared heating source to achieve browning of the potato pieces. The crisp, chip-type snack food product thereby produced is low in calories.

Abstract: A process and apparatus for preparing a cooked food product such as a potato chip without the use of oil. The process and apparatus involves subjecting sliced potato pieces to a sufficient amount of infrared energy to warm the exterior of the sliced potato pieces followed by exposing the sliced potato pieces to microwave energy for a period of time sufficient to warm the interior of the sliced potato pieces and, finally, exposing the sliced potato pieces to a sufficient amount of infrared energy to achieve browning. The crisp, chip-type snack food product thereby produced is low in calories.