Patents Assigned to CHIP'd, Inc.
  • Patent number: 8669792
    Abstract: A driver comprises, an input block for receiving one or more data signals and one or more control signals; a data control block for processing the data signals and the control signals to determine one or more modified control signals, wherein the modified control signal is determined as a function of one or more de-emphasis signals, one or more pre-emphasis signals, and the control signals; and a driver block for receiving the modified control signals and generating one or more output data signals.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: March 11, 2014
    Assignee: Kool Chip, Inc.
    Inventor: Venkata N. S. N. Rao
  • Patent number: 8643516
    Abstract: A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 4, 2014
    Assignee: Kool Chip, Inc.
    Inventor: Venkata N. S. N. Rao
  • Publication number: 20140019921
    Abstract: This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Applicant: Robust Chip, Inc.
    Inventor: Klas Olof Lilja
  • Publication number: 20130223852
    Abstract: An optical communication transmitting device includes a substrate, a first layer with a first optical refractive index formed on the substrate, a waveguide unit formed with a second optical refractive index formed on the first layer, and a second layer with a third optical refractive index covered on the top of the waveguide unit. The second optical refractive index is greater than the first optical refractive index. The second optical refractive index is greater than the third optical refractive index. The waveguide unit is formed from a photo-resistor layer by a high energy light source exposure.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 29, 2013
    Applicant: PHOTON CHIP, INC.
    Inventor: Photon Chip, Inc.
  • Publication number: 20130162293
    Abstract: A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 27, 2013
    Applicant: ROBUST CHIP INC.
    Inventor: ROBUST CHIP INC.
  • Publication number: 20130135740
    Abstract: An optical wavelength dispersion device includes a first substrate, an input unit formed on the first substrate having a slit for receiving an optical signal, a grating formed on the first substrate for producing a diffracted light beams from the optical signal, a first optical reflector formed on the first substrate for reflecting the diffracted light beams from the grating for outputting, and a second substrate covered on the top of the input unit and the grating, wherein the input unit, the grating and the first optical reflector are formed from a photo-resist layer by high energy light source exposure.
    Type: Application
    Filed: July 23, 2012
    Publication date: May 30, 2013
    Applicant: PHOTON CHIP, INC.
    Inventor: Cheng-Hao Ko
  • Publication number: 20130114928
    Abstract: An optical wavelength dispersion device includes a first substrate, an input unit formed on the first substrate having a slit for receiving an optical signal, a grating formed on the first substrate for producing a first light beam form the optical signal for outputting, and a second substrate covered on the top of the input unit and the grating, wherein the input unit and the grating are formed from a photo-resist layer by high energy light source exposure.
    Type: Application
    Filed: July 23, 2012
    Publication date: May 9, 2013
    Applicant: PHOTON CHIP, INC.
    Inventor: Cheng-Hao Ko
  • Patent number: 8427269
    Abstract: An encapsulated electronic device includes a magnetically permeable core structure which is exposed within and coplanar with a flat top surface of the device. A bottom surface of the core may be exposed within the bottom surface of the device. The bottom core surface may be recessed beneath, coplanar with, or protruding from the bottom surface of the device. Alternatively the bottom surface may be encapsulated within the device. A method for manufacturing the exposed core package includes positioning a first component relative to a second component before encapsulating the device. An improved planar magnetic core structure includes internal bevels having a radius greater than or equal to 15% and preferably 25%, 35%, or as much as 50% of the core thickness to reduce concentration of the magnetic field around the internal corners.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 23, 2013
    Assignee: VI Chip, Inc.
    Inventors: Patrizio Vinciarelli, Michael B. LaFleur
  • Patent number: 8427267
    Abstract: An encapsulated electronic device includes a magnetically permeable core structure which is exposed within and coplanar with a flat top surface of the device. A bottom surface of the core may be exposed within the bottom surface of the device. The bottom core surface may be recessed beneath, coplanar with, or protruding from the bottom surface of the device. Alternatively the bottom surface may be encapsulated within the device. A method for manufacturing the exposed core package includes positioning a first component relative to a second component before encapsulating the device. An improved planar magnetic core structure includes internal bevels having a radius greater than or equal to 15% and preferably 25%, 35%, or as much as 50% of the core thickness to reduce concentration of the magnetic field around the internal corners.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 23, 2013
    Assignee: VI Chip, Inc.
    Inventor: Patrizio Vinciarelli
  • Publication number: 20130057321
    Abstract: A driver comprises, an input block for receiving one or more data signals and one or more control signals; a data control block for processing the data signals and the control signals to determine one or more modified control signals, wherein the modified control signal is determined as a function of one or more de-emphasis signals, one or more pre-emphasis signals, and the control signals; and a driver block for receiving the modified control signals and generating one or more output data signals.
    Type: Application
    Filed: November 2, 2012
    Publication date: March 7, 2013
    Applicant: Kool Chip, Inc.
    Inventor: Venkata N.S.N. Rao
  • Publication number: 20130009669
    Abstract: A differential mode driver for driving a differential signal, comprises, at least one unit cell, wherein each of the at least one unit cell comprises at least one resistor and at least one switch resistance and wherein the ratio of the resistances of the at least one resistor and the at least one switch resistance is greater than or equal to a predefined ratio.
    Type: Application
    Filed: September 2, 2011
    Publication date: January 10, 2013
    Applicant: KOOL CHIP, INC.
    Inventor: Venkata N.S.N. Rao
  • Patent number: 8291391
    Abstract: Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains ac
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: October 16, 2012
    Assignee: Advanced Digital Chips Inc.
    Inventors: Jong Sung Lee, Hyeong Cheol Oh, Hyun Gyu Kim, Kwan Young Kim
  • Patent number: 8222772
    Abstract: A method and apparatus for efficiently converting power from an AC line is disclosed. The power converter supplies power to the load, performing power factor correction at nominal and high loads, i.e. above a predetermined output power threshold, and operating in an on-demand burst mode at low loads, i.e. below a predetermined output power threshold, e.g. to supply power in a green mode to supervisory circuitry during a powered off state. The duration of an operating interval during which power conversion takes place may be reduced and varied at low loads as a function of the output power demands to increase overall conversion efficiency. The operating interval may be centered about a peak in the input voltage waveshape for operating intervals that are less than a full rectification period.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: July 17, 2012
    Assignee: VI Chip, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 8090108
    Abstract: A method, system and apparatus of a secure debug interface and memory of a media security circuit and method are disclosed. In one embodiment, a host processor, an external hardware circuit to encrypt an incoming data bit communicated to a debug interface using a debug master key stored at a pointer location of a memory (e.g., the memory may be any one of a flash memory and/or an Electrically Erasable Programmable Read-Only Memory (EEPROM)) and to decrypt an outgoing data bit from the debug interface using the debug master key, and a media security circuit having the debug interface to provide the pointer location of the memory having the debug master key to the external hardware circuit.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: January 3, 2012
    Assignee: Adaptive Chips, Inc.
    Inventors: Amjad Qureshi, Babu Chilukuri
  • Publication number: 20110012859
    Abstract: A resistance type touch panel includes a first substrate, a second substrate and a detection module. The first substrate further includes a touch module at a bottom surface thereof facing the second substrate, in which the touch module has a plurality of conductive blocks having individual signal lines. The second substrate includes a bias-layer module at an upper surface thereof opposing to the touch module by a predetermined spacing. The bias-layer module further includes at least four bias points accounted for at least two voltage biases along two directions. The detection module is electrically coupled with the signal lines of the touch module for realizing all the voltage changes among the conductive blocks.
    Type: Application
    Filed: December 4, 2009
    Publication date: January 20, 2011
    Applicant: ULTRA CHIP INC.
    Inventors: WEN-KUEI LAI, SHIH-HSIN JUAN, CHENG-HSIN LU, WEI-LUNG HUANG, YI-CHEN LO, CHIH-JUNG CHEN
  • Patent number: 7394164
    Abstract: A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the irregular bumps are interspersed in a same pitch. Along a defined line, the widths of the irregular bumps are narrower than the ones of the regular bumps for fine pitch applications. Additionally, the irregular bumps have a plurality of integral probed portions far away the line, top surfaces of which are expanded such that probed points can be defined on the probed portions for staggered probing.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: July 1, 2008
    Assignee: Ultra Chip, Inc.
    Inventors: Bing-Yen Peng, Ho-Cheng Shih
  • Patent number: 7022745
    Abstract: In forming pressure sensitive adhesive microspheres by copolymerizing a non-ionic monomer of an alkyl acrylate or alkyl methacrylate ester of a non-tertiary alcohol and an acid monomer copolymerizable with said non-ionic monomer, an electrolyte is present during the polymerization to promote formation of solid rather than hollow microspheres.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: April 4, 2006
    Assignee: Surf Chip, Inc.
    Inventors: Jong-Shing Guo, Augustin T. Chen, Sharon D. Trembley
  • Patent number: 6964991
    Abstract: Pressure sensitive adhesive compositions having enhanced resistance to water-whitening comprising an aqueous emulsion polymer are disclosed. The polymer comprises the polymerization reaction product of a polymerizable aqueous emulsion comprising: (i) a hydrophobic monomer mixture of at least one alkyl acrylate or alkyl methacrylate ester of an alcohol wherein the alkyl portion of the alcohol is linear or branched and contains at least 4 carbon atoms, and at least one styrenic monomer, wherein the styrenic monomer is up to about 30 wt. % of the total hydrophobic monomer mixture, (ii) at least about 1 wt. % of at least one hydrophilic monomer, (iii) at least about 5 wt.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: November 15, 2005
    Assignee: Surf Chip, Inc.
    Inventors: Augustin T. Chen, Jong-Shing Guo, Tibor Pernecker
  • Patent number: 6864335
    Abstract: In forming pressure sensitive adhesive microspheres by copolymerizing a non-ionic monomer of an alkyl acrylate or alkyl methacrylate ester of a non-tertiary alcohol and an ionic monomer copolymerizable with said non-ionic monomer, non-free radically polymerizable acid is present during the polymerization to promote formation of solid rather than hollow microspheres and to reduce residual unconverted ionic monomer. These microspheres exhibit reduced adhesive transfer in downstream use as a repositionable pressure sensitive adhesive. A water soluble initiator is optionally added to the polymerization mixture after achieving about 90% conversion of the non-ionic monomer to further reduce residual unconverted ionic monomer.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 8, 2005
    Assignee: Surf Chip, Inc.
    Inventors: Jong-Shing Guo, Sharon D. Trembley
  • Patent number: 6820192
    Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: November 16, 2004
    Assignee: Advanced Digital Chips Inc.
    Inventors: Kyung Y Cho, Jong Y Lim, Geun T Lee, Sang S Han, Byung G Min, Heui Lee