Abstract: A modularized probe head for modularly assembling on a probe card is configured for probing a semiconductor wafer under test. The probe head includes a silicon substrate having an active surface and an opposing back surface. The back surface of the silicon substrate is attached on a holder. The silicon substrate has a plurality of peripheral bond pads and contact pads on its active surface. At least a probing chip is mounted on the active surface of the silicon substrate. The probing chip has probing tips and side electrodes. The side electrodes are connected with the contact pads by means of solder material. The peripheral bonding pads of the silicon substrate are connected with a flexible printed circuit for electrically connecting to a multi-layer printed circuit board of a probe card.
Type:
Grant
Filed:
October 8, 2003
Date of Patent:
September 20, 2005
Assignees:
ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.
Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.
Type:
Grant
Filed:
November 20, 2001
Date of Patent:
June 15, 2004
Assignee:
ChipMOS Technologies Inc.
Inventors:
Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
Abstract: A packaging process for improving effective chip-bonding area is disclosed in the present invention. An A-stage liquid paste is formed on a substrate and partially cured to become a B-stage film layer. The B-stage film layer is maintained without fully cured passing through a chip-attaching step and an electrically connecting step. During the molding step, the packing pressure for the molding compound (1000 psi˜1500 psi) is larger than the chip attaching pressure for enabling the B-stage film layer to be closely compressed in order to improve effective chip-bonding area. The B-stage film layer and the molding compound are cured simultaneous in the molding step.
Type:
Application
Filed:
November 26, 2003
Publication date:
June 3, 2004
Applicants:
ChipMOS Technologies (Bermudea) Ltd., ChipMOS TECHNOLOGIES INC.
Abstract: A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.
Type:
Application
Filed:
August 20, 2002
Publication date:
February 26, 2004
Applicant:
ChipMOS Technologies (Bermuda) Ltd. and ChipMOS TECHNOLOGIES INC.
Inventors:
S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
Abstract: A probe card with full wafer contact configuration comprises a back plate and a plurality of modular multiplayer ceramic wiring boards coplanarly mounted on the back plate. The total size of the modular multilayer ceramic wiring boards is larger than that of a wafer under test in order to fully contact all the bonding pads of the wafer under test. The modular multilayer ceramic wiring boards can be manufactured separately according to various locations. Thus, the manufacturing cost is reduced and yield is improved and lead time is shortened.
Type:
Application
Filed:
July 19, 2002
Publication date:
January 22, 2004
Applicants:
ChipMOS Technologies (Bermuda) Ltd., ChipMOS TECHNOLOGIES INC.
Inventors:
S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
Abstract: A modular probe card assembly comprises a silicon substrate with probes modularly assembled on a main board. At least a socket is installed around silicon substrate and electrically connects to probe needles by a flexible printed wiring film. A plurality of detachable coaxial wires electrically connect sockets with the main board for achieving variability of connecting paths during manufacturing. Thus, the probe card assembly has the effect of adjustable amendment and is suitable for high speed testing.
Type:
Grant
Filed:
July 19, 2002
Date of Patent:
September 16, 2003
Assignees:
ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.
Type:
Grant
Filed:
November 28, 2001
Date of Patent:
August 12, 2003
Assignee:
ChipMOS Technologies Inc.
Inventors:
An-Hong Liu, Yuan-Ping Tseng, Y. J. Lee
Abstract: A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.
Abstract: A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are butted together to save space. The bonding pads for the lower IC chip or chips are placed along the edges not butted with one another. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be placed at the top of the IC chips away from the ball grid array.
Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are stacked to save space. The bonding pads for the lower IC chip or chips are placed along the edges where the pads are not masked by the stacking of the upper chip or chips. When there are more than one chip at each level of the stacking, the IC chips at each level are butted with each other to further save space. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be inserted at the bottom of the IC chips away from the stacking surface.