Patents Assigned to ChipMOS Technologies (Bermuda)
  • Patent number: 7847414
    Abstract: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 7, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Patent number: 7843054
    Abstract: A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 30, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventor: Shih-Wen Chou
  • Patent number: 7842550
    Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 30, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Chun-Ying Lin, Geng-Shin Shen, Po-Kai Hou
  • Patent number: 7834432
    Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: November 16, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd
    Inventors: Wu-Chang Tu, Geng-Shin Shen
  • Patent number: 7812432
    Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: October 12, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Po-Kai Hou, Chi-Jin Shih
  • Patent number: 7803667
    Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 28, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin
  • Patent number: 7803666
    Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 28, 2010
    Assignees: ChipMOS Technologies INc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin
  • Patent number: 7795079
    Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 14, 2010
    Assignees: ChipMoS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin
  • Patent number: 7790514
    Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 7, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Chun-Ying Lin
  • Patent number: 7749806
    Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 6, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Patent number: 7741149
    Abstract: A chip package structure includes a chip, a lead frame, first and second bonding wires, an upper encapsulant, a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface, and chip bonding pads disposed on the active surface. The lead frame having an upper surface and a lower surface includes a die pad, leads, and at least a bus bar. The back surface of the chip is adhered to the die pad. The leads surround the die pad. The bus bar is disposed between the die pad and the leads. The first bonding wires are connected to the chip bonding pads and the bus bar. The second bonding wires are connected to the bus bar and the leads. The upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires, and the second bonding wires.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: June 22, 2010
    Assignee: ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yong-Chao Qiao, Yan-Yi Wu, Jie-Hung Chiou
  • Patent number: 7732911
    Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: June 8, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Tsung-Lung Chen, Ming-Hsun Li
  • Patent number: 7723853
    Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: May 25, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yu-Tang Pan, Cheng-Ting Wu, Shih-Wen Chou, Hui-Ping Liu
  • Patent number: 7696443
    Abstract: An electronic device comprises a substrate and at least a warped spring connector. The substrate has a signal bonding pad and a ground plane. The warped spring connector is disposed on the substrate and is connected to the bonding pad. The warped spring connector includes at least a ground lead electrically connected to the ground plane, a dielectric layer on the ground lead, and a transmitting lead on the dielectric layer. The transmitting lead is bonded to the bonding pad. The ground lead is isolated from and close to the transmitting lead to solve cross-talk and noise problem. Furthermore, the coefficient of thermal expansion of the transmitting lead is different from that of the dielectric layer or the ground lead such that the warped spring connector has a suspending end suspending away from the substrate.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: April 13, 2010
    Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
    Inventors: Yi-Chang Lee, An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Yao-Jung Lee
  • Patent number: 7683462
    Abstract: A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 23, 2010
    Assignee: ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Jie-Hung Chiou, Yong-Chao Qiao, Yan-Yi Wu
  • Patent number: 7651886
    Abstract: A semiconductor device including a circuit structure and a protective layer is provided. The circuit structure has multiple contacts. The protective layer is located on the circuit structure and has multiple openings and multiple protrusions, wherein the contacts are exposed by the openings and the protrusions are located on the contacts.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 26, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventor: Jiun-Heng Wang
  • Patent number: 7648902
    Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: January 19, 2010
    Assignee: ChipMOS Technologies (Bermuda) Ltd.
    Inventor: Xuan-Feng Lu
  • Patent number: 7642137
    Abstract: A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: January 5, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Chun-Ying Lin, Ya-Chi Chen, Yu-Ren Chen, I-Hsin Mao
  • Patent number: 7638880
    Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 29, 2009
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Patent number: 7615853
    Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 10, 2009
    Assignees: CHIPMOS Technologies Inc., CHIPMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, Wu-Chang Tu