Abstract: A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) signals in cache-based personal computer systems thereby enabling the system to accommodate a plurality of microprocessor devices.

Abstract: An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics address to a system address within the system memory. The invention initially partitions the system memory into a dedicated system memory for use by the graphics controller and a non-dedicated system memory for use by the central processing unit. The dedicated system memory corresponds to a base assigned memory within the graphics memory address map, and the non-dedicated system memory corresponds to a portion of the graphics memory address map excluding the base assigned memory. If the graphics address is within the base assigned memory, the graphics address is translated to a corresponding system address within the dedicated system memory.

Abstract: The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.

Abstract: A system is provided that allows for the synchronous operation of a memory controller within a computer when the local bus clock has become inactive for a predetermined period of time. The system includes a circuit that senses the presence of the local bus clock and dependent upon whether the local bus clock is active or inactive causes a switching circuit to switch to a second clock signal that is independent of the local bus clock to run the memory controller. In one embodiment, a pixel clock signal is utilized to run the memory controller when the local bus clock signal is not active.

Abstract: A system which allows for the generation of grayscale video signals from color graphics images to grayscaling display devices receiving digital signals. The system is implemented advantageously in packed pixel color graphics modes of a video graphics array sysem utilized in a personal computer. The system is preferably implemented in a software program to decrease the number of hardware components, save circuit board space, consume less power and reduce complexity in the circuitry in the personal computer.

Abstract: A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.

Abstract: A direct memory access (DMA) controller (4) utilizes a segmented counter (220). A first, byte counter portion (330) of the counter is initialized with a preselected value and decremented for each byte transfer. After the byte portion of the counter reaches the preselected value it decrements a second, block portion (332) of the counter which is initialized based upon the amount of data to be transferred. When both the byte counter and the block counter reach zero the data transfer is completed.

Abstract: An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions at a time, a first ROM connected to the register for decoding the first byte into control signals for operation of said microprocessor. One of these control signals is generated whenever the portion of the second instruction byte is required. The organization also has a second ROM connected to the register for decoding the portion of the second byte into control signals. Connected to said first and second ROMs is a multiplexer which selects the decoded second byte control signals for operation of the microprocessor responsive to the first ROM control signal.

Abstract: A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.

Abstract: An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.

Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Abstract: A method and apparatus for improving the quality of a color-to-gray scale conversion is disclosed. A table is generated providing a visually correct conversion of all possible background/foreground colors. This table is then stored. In operation, after the attribute byte describing the foreground and background colors is retrieved from memory, it is used to access the stored conversion table, wherein its gray scale equivalent is stored. The stored equivalent is then used to generate the gray scale LCD display. In other embodiments, multiple copies of the table are stored, making multi-frame operations very efficient in operation.

Abstract: A system for assisting the scanning of a keyboard associated with a personal computer. The system comprises a logic circuit which interacts with the microcontroller and the keyboard to reduce power consumption by the personal computer as well as freeing the microcontroller to do other tasks. The logic circuit "interrupts" the microcontroller whenever keyboard activity is detected. An image RAM stores a pattern of current key closures to be compared in subsequent keyboard scans. A subsequent miscompare between the keyboard and the Image RAM indicates that keyboard activity has occurred. When no keys are pressed, scanning may be stopped. Any key closure will then generate an interrupt, and the microcontroller will restart scanning.

Abstract: A instruction fetch circuit which allows portions of the instruction to be decoded and executed independently. The invention includes a first register for storing a digital data word having first and second bytes. The first register provides first and second outputs of the first and second digital bytes respectively. A first multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register and providing a first intermediate output corresponding thereto. A second multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register or the first intermediate output of the first multiplexer circuit and providing a second intermediate output corresponding thereto. Control circuitry is included for selectively activating the first register and the first and second multiplexer circuits to present portions of the instruction for decoding. Additional multiplexer circuits are included to handle larger instructions.

Abstract: VGA controller interface circuitry that allows the VGA controller to reduce the cycle time of a write to the controller below the default write cycle time, resulting in a significant improvement of the controller's performance. The controller interface circuitry uses a Zero Wait State control signal on the system bus to reduce the cycle time by overriding the default cycle time for a memory write, unless the /Ready signal is asserted by the controller.

Abstract: An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.

Abstract: The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be adjusted under program control.

Abstract: An efficient and optimized FIFO memory for use in a bus master system utilizes a multiplexing clock from which control signal defining bus cycles on asynchronous system and local buses. The FIFO facilitates interleaved access by system and local buses to support high speed data transfers from devices on one bus to the other bus.

Abstract: A VGA controller with a read-modify-write cycle implemented therein is provided. By implementing the read-modify-write cycle in hardware, and by reducing the data for such operations to a single address source, read-modify-write operations can be performed in a single cycle, as opposed to separate read and write cycles, with a consequent improvement in overall operating speed.

Abstract: Display control logic for a terminal controller with support for such features as windows and interlace. A display list processor (DLP) (20) communicates with a program memory (12) containing DLP instructions, a display memory (12) containing character codes and attributes for the display, and a font memory (13). As the DLP program executes, it causes accesses to the display memory and brings in character codes and attributes for ultimate display on the screen. These character codes and attributes, as well as information representative of the scan line are input to a video data queue (95). The queue entries are clocked out of the queue by a character clock (170) and are used to generate addresses to font memory. Bitmaps from font memory are read into a dot shifter (190). The DLP instruction set includes a DISPLAY STRING instruction which allows a portion of a scan line to be built up by specifying the length of the scan line segment and the starting address in memory.