Abstract: A system which allows for the generation of grayscale video signals from color graphics images to grayscaling display devices receiving digital signals. The system is implemented advantageously in packed pixel color graphics modes of a video graphics array sysem utilized in a personal computer. The system is preferably implemented in a software program to decrease the number of hardware components, save circuit board space, consume less power and reduce complexity in the circuitry in the personal computer.

Abstract: A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.

Abstract: The present invention provides a microprocessor with a special Operation Capture Facility (OCF) mechanism which enables "faulting" whenever there is (a) a memory access request to any one of a specified plurality of blocks of memory (b) a request to access any one of a plurality of specified I-O ports or (c) any one of a specified plurality of interrupts is activated. This OCF mechanism includes a plurality of special registers which store either (a) an I-O port address, (b) a memory address or (c) an interrupt number. Mask registers are provided which (1) mask bits in the special register, thereby providing the ability to fault on an entire block of I-O access requests or upon activation of any one of a block of interrupts and (2) indicate which type of interrupts should be faulted and to indicate whether I-O should be faulted on a byte, word or double word.

Abstract: A direct memory access (DMA) controller (4) utilizes a segmented counter (220). A first, byte counter portion (330) of the counter is initialized with a preselected value and decremented for each byte transfer. After the byte portion of the counter reaches the preselected value it decrements a second, block portion (332) of the counter which is initialized based upon the amount of data to be transferred. When both the byte counter and the block counter reach zero the data transfer is completed.

Abstract: An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions at a time, a first ROM connected to the register for decoding the first byte into control signals for operation of said microprocessor. One of these control signals is generated whenever the portion of the second instruction byte is required. The organization also has a second ROM connected to the register for decoding the portion of the second byte into control signals. Connected to said first and second ROMs is a multiplexer which selects the decoded second byte control signals for operation of the microprocessor responsive to the first ROM control signal.

Abstract: A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.

Abstract: An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.

Abstract: The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Abstract: A method and apparatus for improving the quality of a color-to-gray scale conversion is disclosed. A table is generated providing a visually correct conversion of all possible background/foreground colors. This table is then stored. In operation, after the attribute byte describing the foreground and background colors is retrieved from memory, it is used to access the stored conversion table, wherein its gray scale equivalent is stored. The stored equivalent is then used to generate the gray scale LCD display. In other embodiments, multiple copies of the table are stored, making multi-frame operations very efficient in operation.

Abstract: A system for assisting the scanning of a keyboard associated with a personal computer. The system comprises a logic circuit which interacts with the microcontroller and the keyboard to reduce power consumption by the personal computer as well as freeing the microcontroller to do other tasks. The logic circuit "interrupts" the microcontroller whenever keyboard activity is detected. An image RAM stores a pattern of current key closures to be compared in subsequent keyboard scans. A subsequent miscompare between the keyboard and the Image RAM indicates that keyboard activity has occurred. When no keys are pressed, scanning may be stopped. Any key closure will then generate an interrupt, and the microcontroller will restart scanning.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: Two methods and apparatus for reducing power consumption in battery powered computers are disclosed. The first places the computer in a sleep mode whenever a certain data input function is called. The second applies statistical analysis to calls to another data input function. By measuring the number of times the computer has tried to read data from the keyboard over the past predefined period, the variance between the high and low number of calls over the present and preceding time periods, and whether the number of times the computer has tried to read data has both exceeded the present limit and remained within the preset variance limit for a predefined minimum time, the desirability of activating a sleep mode for the computer can be determined.

Abstract: A instruction fetch circuit which allows portions of the instruction to be decoded and executed independently. The invention includes a first register for storing a digital data word having first and second bytes. The first register provides first and second outputs of the first and second digital bytes respectively. A first multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register and providing a first intermediate output corresponding thereto. A second multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register or the first intermediate output of the first multiplexer circuit and providing a second intermediate output corresponding thereto. Control circuitry is included for selectively activating the first register and the first and second multiplexer circuits to present portions of the instruction for decoding. Additional multiplexer circuits are included to handle larger instructions.

Abstract: A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequence. Although the amount of time taken for actually refreshing the memory is the same, the time needed for arbitration to obtain control of the necessary busses is reduced, giving an overall savings of time. In the hidden refresh mode, a refresh is done, but no hold signal is sent back to stop the CPU while the refresh is being done. Circuitry is provided which allows local memory accesses, but holds other memory accesses until the refresh is completed. Thus, local memory accesses, which expect data quickly, are not inhibited and other memory accesses, which the CPU expects may take some time, can be held up without the CPU knowing.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: VGA controller interface circuitry that allows the VGA controller to reduce the cycle time of a write to the controller below the default write cycle time, resulting in a significant improvement of the controller's performance. The controller interface circuitry uses a Zero Wait State control signal on the system bus to reduce the cycle time by overriding the default cycle time for a memory write, unless the /Ready signal is asserted by the controller.

Abstract: An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control segment a limit exception occurs.

Abstract: An efficient and optimized FIFO memory for use in a bus master system utilizes a multiplexing clock from which control signal defining bus cycles on asynchronous system and local buses. The FIFO facilitates interleaved access by system and local buses to support high speed data transfers from devices on one bus to the other bus.

Abstract: The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be adjusted under program control.