Abstract: The present invention provides a transceiver apparatus that permits miniaturization even when the antenna thereof is an unbalanced circuit and the transmitter circuit section and receiver circuit section thereof are balanced circuits. The transceiver apparatus is constituted comprising: a semiconductor integrated circuit device that mounts on the same semiconductor chip a balanced receiver circuit 41 for receiving a received signal as a differential input and balanced transmitter circuit 52 for outputting a transmitted signal as a differential output, and that has at least two terminals 71,72 connected to connecting nodes that connect the balanced receiver circuit 41 and the balanced transmitter circuit 52; first and second capacitors C2,C3 connected to the terminals 71, 72 respectively; an external inductor L1 connected to the first and second capacitors C2, C3; a band pass filter 2 and an antenna 1 coupled to the first capacitor C2; and a third capacitor C1 connected to the second capacitor C3.

Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).

Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.

Abstract: A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.

Abstract: A method of generating a graphical image, such as a font, is described in which expansion data for an image portion that is not to be written is never added to source data for such portion.

Abstract: A circuit suitable for use in electronic systems which utilize Synchronous Dynamic Random Access Memory (SDRAM), and method according to the present invention comprises an application-specific integrated circuit. When a burst command is initiated by the memory controller, causing the SDRAM to perform a data transfer into or out of memory which require many consecutive clock cycles to complete, the circuit recognizes the SDRAM commands as those commands appear on the instruction bus. The circuit then analyzes other operations which are pending and which might be performed during otherwise unusable time periods while the burst operation is being performed by the SDRAM. The circuit issues instructions to initiate and complete these operations prior to the SDRAM command being completed.

Abstract: A text image stretching system in a VGA for a plurality of text image font sizes comprises a plurality of cell line replication registers having inputs and outputs, the plurality of cell line replication registers formed into groups corresponding to one of the plurality of text image font sizes, each cell line replication register having a plurality of bits, the inputs of the plurality of cell line replication registers connected to the VGA to receive cell line replication information for storage in the plurality of cell line replication registers, a multiplexer having data inputs, first and second select inputs and a plurality of outputs, each of the data inputs connected to one of the plurality of bits of the plurality of cell line replication registers, the first and second select inputs decoded to select one bit from each of the cell line replication registers in one of the groups of the cell line replication registers to form a cell line replication code for output on the plurality of outputs, a repeat c

Abstract: A switch array decoding circuit, suitable for use in a keyboard, and method according to the present invention comprises a matrix of row lines and column lines. Switches from the array are connected between intersections of the row lines and column lines. The row lines and column lines are connected to I/O pins leading to one or more components containing the decoder circuitry. The decoder circuitry first simultaneously drives the row lines while sensing the column lines. When a switch closure is detected, the states of all column lines are simultaneously sensed. This operation determines the column position(s) of the one or more switches being closed. The column lines are then simultaneously driven while simultaneously sensing the row lines. This operation determines the row position(s) of the one or more switches being closed. The row and column drive and sense order may be reversed.

Abstract: In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority.

Abstract: A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) signals in cache-based personal computer systems thereby enabling the system to accommodate a plurality of microprocessor devices.

Abstract: An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics address to a system address within the system memory. The invention initially partitions the system memory into a dedicated system memory for use by the graphics controller and a non-dedicated system memory for use by the central processing unit. The dedicated system memory corresponds to a base assigned memory within the graphics memory address map, and the non-dedicated system memory corresponds to a portion of the graphics memory address map excluding the base assigned memory. If the graphics address is within the base assigned memory, the graphics address is translated to a corresponding system address within the dedicated system memory.

Abstract: The invention pertains to the adaptive vertical stretching of an original image so that the resulting stretched image optimally fits within the vertical boundary of a display having a fixed number of pixel lines. A line replication state machine provides the stretching of the original image, while a line replication generator preferably generates new line replication numbers by sequentially incrementing an initial line replication number in an integer by integer fashion. A display image measuring device provides a display fit status to the state machine, enabling the state machine to determine whether a resulting stretched image fits within the display exceeded the vertical height of the display. The state machine toggles between two types of line stretching that gives a stretched image closely fitted to the maximum image size available in an applicable display.

Abstract: The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.

Abstract: A ring oscillator is embedded into the same silicon wafer as the functional circuits. The output of the ring oscillator and a display clock signal are both directed into seperate inputs of a multiplexer which is controlled by the computer BIOS. When the BIOS desires to read the ring oscillator frequency, the multiplexer is switched, thus providing the output of the ring oscillator to the display status register. The resulting frequency may be used to optimize clock speeds.

Abstract: A system is provided that allows for the synchronous operation of a memory controller within a computer when the local bus clock has become inactive for a predetermined period of time. The system includes a circuit that senses the presence of the local bus clock and dependent upon whether the local bus clock is active or inactive causes a switching circuit to switch to a second clock signal that is independent of the local bus clock to run the memory controller. In one embodiment, a pixel clock signal is utilized to run the memory controller when the local bus clock signal is not active.