Abstract: A method for communicating packetized data over a communications link having a predetermined format including a framing using a channel bank having a time division multiplexing addressing scheme is disclosed in which a plurality of channel units may generate packetized data and the communications link may be allocated to a channel unit that is currently sending data over the communications link. The next sender of packetized data over the communications link may be determined by a system distributed over the plurality of channel units so that each channel unit independently determines whether it is the next sender. The communications link may be allocated to the channel unit that is the next sender of packetized data after the current sender of packetized data so that the time division multiplexing addressing scheme of the channel bank is ignored and the channel bank communicates packetized data. An apparatus for communicating packetized data over a channel bank is also disclosed.

Abstract: The invention provides a method and system for auto-sensing LMI protocols in frame relay networks. When a router is first coupled to a frame relay network, it automatically configures the local management interface (LMI) to use one of a selected set of possible LMI protocols, by generating a set of protocol requests for a plurality of protocols, and by thereafter simultaneously listening for protocol responses from the configuration server. Multiple valid responses from the configuration server are assigned priority in response to which valid response is last to arrive.

Abstract: A pluggable port adapter is used for connecting PCI devices to a host system through a PCI local bus while also adding functionality to the host system. The port adapter communicates with the host system through a port adapter/host interface that includes the PCI local bus and an auxiliary bus. The auxiliary bus is used for controlling the additional circuitry on the port adapter. A PROM on the adapter card is used for identifying the port adapter type, serial number and hardware revision. The auxiliary bus is used for conducting JTAG testing and is used by the host system to program logic devices on the port adapter. The logic devices can be reprogrammed in the field by the host system to repair bugs and to enhance performance and/or functionality. A power control circuit on the port adapter is controlled by the auxiliary bus for conducting hot swap operations.

Abstract: A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.

Abstract: In a data transmission system having a first and a second data transmission device and a transmission line that is not terminated, a method of minimizing signal reflection along the transmission line is described that includes the step of connecting the first and second data transmission devices to the transmission line such that the distance between the first and second data transmission devices is substantially proportional to a wavelength of a predetermined frequency. Data to be transmitted from the first data transmission device to the second data transmission device via the transmission line are encoded in the first data transmission device such that energy of the encoded data is substantially concentrated around the predetermined frequency to minimize the signal reflection without terminating the transmission line. A data transmission system with minimized signal reflection is also described.

Abstract: A switch in an asynchronous transfer mode system utilizes an early packet discard (EPD) scheme and discards all but the end-of-packet cell of packets that are expected to prevent other partially transmitted packets from being transmitted through the switch. The switch also utilizes an integrated tail packet discard (I-TPD) scheme and, once a cell of a packet has been discarded for any reason, discards all of the remaining cells of the packet except the end-of-packet cell. Each of the EPD and the I-TPD schemes retain the last cell of a packet in order to maintain packet boundaries. Further, they each set the loss-priority of the end-of-packet cell to high, to increase the likelihood that the cell will be transmitted through the remaining switches in the route to the station to which the packet is directed. When the end-of-packet cell is received, the switch retains the cell unless its maximum queue limit is exceeded, and resets any associated early or tail packet discard flag.

Abstract: An encapsulation mechanism efficiently transports packets between ports of different switches in a network on the basis of, inter alia, virtual local area network (VLAN) associations among those ports. The switches are preferably interconnected by a novel interswitch link (ISL) mechanism that appends ISL destination and source information, along with ISL error detection information, to VLAN-modified packets. The ISL mechanism keeps the VLAN associations of the packets intact during transfer between the switches in accordance with a high-performance switching bus architecture.

Abstract: An address translation mechanism quickly and efficiently renders forwarding decisions for data flames transported among ports of a high-performance switch on the basis of, inter alia, virtual local area network (VLAN) associations among the ports. The translation mechanism comprises a plurality of forwarding tables, each of which contains entries having unique index values that translate to selection signals for ports destined to received the data frames. Each port is associated with a unique index value and a VLAN identifier to facilitate multicast data transfers within the switch at accelerated speeds and addressing capabilities.

Abstract: A communication interface with an expandable multilane cell bus that enables conversion of communication traffic received over a set of low speed or narrow band communication links according to a first communication protocol into a series of communication cells according to a second communication protocol. The cell bus enables concentration of the communication cells for transfer over a high speed communication link according to the second protocol. The communication interface includes a cell bus master that polls slave service modules while transferring communication cells to the service modules over a unidirection transmit portion of the cell bus and while receiving communication cells over a unidirection receive portion of the cell bus.

Abstract: A destination station receives from a network a data packet that is transmitted as a plurality of cells and separately encodes each of the received cells, to produce associated, individual c-bit partial CRC remainders, where c is the number of bits in the CRC remainder associated with the packet. These partial CRC remainders correspond to the respective contributions that the cells make to the packet CRC pattern. The encoder appends the partial CRC remainders to the cells, and the station then stores them in an associated memory and links the individual cells to previously stored cells from the same packet with pointers. Once all the cells of a packet are encoded and stored, the destination station retrieves appended partial CRC remainders from the memory, and provides the remainders to a partial CRC encoder. The encoder manipulates the partial remainders and produces a packet CRC remainder.

Abstract: A network that implements a network management protocol. The network comprises a network manager coupled to a plurality of network nodes. Each network node has a network address to which the network manager addresses network management messages for controlling the configuration of the network nodes. The plurality of network nodes include a first network node. The first network node includes a plurality of management agents and a message forwarding circuit coupled to the management agents, wherein the network manager transmits a management message to the network address of the first network node and the message forwarding circuit forwards the management message to a first management agent specified by the management message.

Abstract: A frame based traffic policing system that determines if incoming data cells are conforming or non-conforming according to the a traffic contract. The frame based traffic policing system first detects a cell at the beginning or end of a frame and determines if the frame conforms with a traffic contract. If the cell does not exceed the parameters of the traffic contract, then the frame based traffic policing system deems the cell as conforming. If the cell was the first cell of a frame, then frame based traffic policing system treats all the remaining cells in the frame as conforming or non-conforming depending upon if the first data cell was conforming or non-conforming. If the cell was the last cell of a frame, then frame based traffic policing system treats all the cells of the following frame as conforming or non-conforming depending upon if the last cell of a previous frame was conforming or non-conforming.

Abstract: A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secondary bus, the second bridge is configured to only act as master on the primary bus and as a target on the secondary bus. The determination of which data path is chosen is not made by the bridges and thus the bridges do not bias the direction of transmissions to one bus or to the other bus.

Abstract: A method for establishing and maintaining virtual network domains in a segmented computer network having a first domain and a second domain. A first table entry for a first endstation in a first forwarding table of a first switching fabric circuit is created. The first table entry includes domain information specifying that the first endstation is in the first domain and port information specifying that the first endstation is coupled to a first port. A packet having the first endstation as a source is received by the first port of the first switching fabric circuit, and a destination for the packet is determined. If the packet specifies a second endstation of the first domain as the destination, the packet is forwarded to the second endstation. If the destination for the packet specifies more than one endstation, the domain of the source of the packet is determined, and the packet is forwarded to the specified endstations of the first domain.

Abstract: A switching fabric circuit that provides on-the-fly switching of packets, an expandable number of ports, and the interconnection of heterogeneous LAN segments. The switching fabric circuit includes a switching link that comprises a switching bus and a plurality of packet processors, wherein each packet processor is coupled between the switching bus and a LAN segment. The switching bus is a time division multiple access (TDMA) bus, and arbitration for switching bus access is distinct from arbitration for access to the ports of the switching fabric circuit. Switching bus arbitration is done according to one of two priority levels, wherein high priority requests are guaranteed access to the switching bus during a synchronization period in which the high priority requests are made. This provides for guaranteed throughput and on-the-fly switching of packets. Port arbitration may be either uniport port arbitration or multiport port arbitration.

Abstract: A reliable transport protocol, suitable for routing protocols, that works with unicast transmission and multicast transmission, and an improved routing protocol based thereon. Multicast transmissions can be interspersed with unicast transmissions in situations where some of the receivers have received all of the packets sent to them and others have not. A mechanism to deliver multicast packets quickly to some receivers, even when there are unacknowledged packets pending for other receivers. When a packet is multicast from a sender node to all of its neighbors, the sender puts the packet on a queue for each neighbor and retransmits the packet if an acknowledgement has not been received within a predetermined period of time. If the packet is retransmitted, it is transmitted as a unicast. The invention takes advantage of the fact that the sender already has to maintain state information to determine who has not received its packets.

Abstract: An improved method and apparatus for routing data transmissions among computer networks. The computer networks are interconnected with a series of gateway circuits. Each gateway identifies all destination computers to which it is connected and identifies the path or paths to each destination computer. For each identified path, the gateway stores the topological delay time for a transmission, the path bandwidth for the narrowest bandwidth segment of a path and a number corresponding to the reliability of the path. When a transmission is received, the gateway examines the various paths in accordance with a predetermined algorithm which also considers the channel occupancy of each path to determine a best path for transmision. The data transmission is then directed over the best path. If more than one path exists, the data may be directed in multiplex fashion over two or more paths with the amount of data on each path being related to the quality of the path.