Abstract: A cellular communication system in which dedicated repeater controller transceivers are included in base stations and wireless base stations. The repeater controller transceivers are configured to operate on a different channel as compared to communications received by or transmitted directly from mobile terminals. By utilizing a dedicated channel for communications between the base stations and wireless base stations, the contention areas formed by overlapping cell areas is effectively eliminated. The different channels may be based on differences in parameters such as frequency and/or data encoding techniques.

Abstract: A cellular communication system in which dedicated repeater controller transceivers are included in base stations and wireless base stations. The repeater controller transceivers are configured to operate on a different channel as compared to communications received by or transmitted directly from mobile terminals. By utilizing a dedicated channel for communications between the base stations and wireless base stations, the contention areas formed by overlapping cell areas is effectively eliminated. The different channels may be based on differences in parameters using infrared communication techniques.

Abstract: A correlation system for use in wireless direct sequence spread spectrum systems includes a RF down converter which receives an encoded RF signal and generates therefrom analog in-phase (I) and quadrature (Q) signal components. These components are digitized and the digitized signals are then passed to each of the high precision correlator circuit and a low precision correlator circuit. The low precision correlator circuit consist of a bank of a plurality of low precision correlators which receive the I and Q signal components as inputs and correlates the same with progressively phase shifted or delay pseudo noise (PN) codes. A low precision correlation circuit locks on to the appropriate PN code phase shift or delay and applies the same as a reference PN code to the high precision correlation circuit for data acquisition and demodulization.

Abstract: In accordance with the invention, a method and structure are provided for obtaining a ratio of M/(2.sup.N +K) by feeding various carry-out (and/or complemented carry-out) signals from full-adders back to various frequency control inputs of the full-adders to modify the denominator of the division ratio. By doing this, K additional or fewer counts are accumulated during each cycle. Thus, the denominator can be changed from 2.sup.N to 2.sup.N +K, where K can be either positive or negative to obtain the desired M/(2.sup.N +K) ratio.

Abstract: For use in a communications network capable of establishing a bonded call between first and second endpoints using at least two bonded communication channels, a subsystem for preserving a relative latency of the at least two bonded communication channels to allow the bonded call to be transferred to a third endpoint. The subsystem includes: (1) a buffer depth index detection circuit that detects learned values of buffer depth indices associated with the bonded call and stored at a first location and (2) a buffer depth index transmission circuit, coupled to the buffer depth index detection circuit, that transmits the learned values to a second location accessible by the third endpoint to allow the bonded call to be transferred to the third endpoint without requiring the third endpoint to relearn the values.

Abstract: A point-to-multipoint or two-way communications system is provided by a nodal transmitter located in a node with a plurality of nodal antennas radiating different polarization signals about the node. The system includes subscriber stations with directional antennas adapted to receive signals radiated from the nodal transmitter. The system may additionally include capability for transmitting and radiating subscriber signals to the nodal transmitter location for two-way communications.

Abstract: A digital system for Bit Error Rate Testing (BERT) of test transmission lines and/or devices and including a test equipment coupled to at least one transmission line for transferring digital information between the test equipment and a company office, a bit error generator coupled to the transmission lines for generating test patterns, a device for storing a plurality of predetermined profiles, each profile having associated therewith at least one parameter for measuring the integrity of the test equipment or the transmission lines, the parameters including one of the generated test patterns.

Abstract: The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied based on actual network traffic loading and congestion encountered.

Abstract: A communication network having a plurality of routers, each connected to a host system by a LAN network and interconnected by a switched network, the common network using a shared or common IP and MAC address in the routers forming a subnet. Host systems on the same subnet use the shared or common IP address as their default gateway address when accessing host systems on another subnet.

Abstract: A reduced size field effect transistor is disclosed which has a substrate with a body of semiconductor material having an active region on one surface thereof, and a common conductor located in remote insulated relation to the one surface of the semiconductor body, a pair of source electrodes, a drain electrode and a gate electrode located on the one surface, with the drain electrode having drain fingers located on opposite sides of each of the source electrodes and an air bridge overlying the source electrodes and interconnecting the drain fingers located on opposite sides of each of the source electrodes, the gate electrode having a connection pad at one side thereof and a manifold extending between the source electrodes, and having gate fingers extending between the drain fingers and the source electrodes, and conductive connections between the source electrodes and the common conductor.

Abstract: A universal adapter bracket for installing standard form factor adapter cards such as PCI cards into larger expansion slots of a communications device, such as a router or switch. The adapter bracket has a front face with angled flanges forming an aperture for accepting standard PC brackets, an upper flange with conductive spring clips or foam gasket material, a lower flange for securing a carrier card to the adapter bracket, and fasteners on the front face of the adapter bracket for securing and grounding the adapter bracket to the communications device.

Abstract: A data transfer flow control system for a packet communications system includes a plurality of nodes interconnected by transmission links. The rate at which a sender node transmits information to a destination node in a network is modified in accordance with congestion information returned to the sender node from nodes along the path of the transmission or from the information receiver. The rate change for information being sent from the sender node is modified based upon the amount of elapsed time occurring since the last rate change of the same type. In first and second examples, the rate change is implemented in accordance with exponential and linear relationships, respectively, between the modified flow rate and the elapsed time since the last rate change.

Abstract: In high speed cell switching networks, a Call Admission Control (CAC) procedure is performed on each connection according to a specified Traffic Descriptor. A mandatory parameter of the Traffic Descriptor is the Peak Cell Rate (PCR), associated with a Cell Delay Variation Tolerance (CDVT). Connections which specify a high CDVT value may potentially send into the network bursts of cells at a rate much higher than the declared Peak Cell Rate, which may lead to congestion in cell buffers of intermediate network nodes. Guaranteeing the Quality of Service (QoS) for such connections may require the reservation of a high amount of resources in the network, leading to poor utilization of those resources.

Abstract: Backup peers in an asymmetrically organized computer network are organized into a "pool" of available devices that are activated as necessary. The network comprises a set of remote peers and a set of local peers directly associated with a central computational facility, the local peers facilitating connection between the remote peers and the central facility. During the capabilities exchange, the "primary" local peer to which the remote peer connects provides a list of backup peer devices to the remote peer. If the primary peer fails (or if the rate of message exchange falls below some predetermined threshold), the remote peer can use the backup information to access a backup peer from the pool. The invention allows each backup peer to be assigned to multiple remote peers, with the total number of backup peers determined by aggregate backup utilization (rather than simply assigning an individual backup peer to each primary peer regardless of whether such a high level of redundancy is justified).

Abstract: The present invention includes a method and apparatus for prioritizing and scheduling ATM cells that are competing for a given time slot for transmission onto a network. A segmentation and reassembly controller establishes a data structure within a memory. The preferable data structure includes a virtual connection time table and a virtual connection parameter table that use linked lists to index to one another. The segmentation and reassembly (SAR) controller includes a sorter for determining the priority of the ATM cells and selecting one for a given time slot and a microcode engine to compute next scheduled time slot and adjust the virtual connection parameter table for a given virtual connection. Coupled to the microcode engine is a random access memory for storing microcode programs so that the SAR may be programmed to prioritize and schedule in a different manner.

Abstract: A subsystem for communicating a private network signalling message over a packet network and bridges for communicating a Media Access Control (MAC) layer frame over an isochronous channel and for communicating an isochronous signalling frame over a nonisochronous network.

Abstract: An intermediate station produces, for an altered packet that includes multiple cells from a received packet and one or more altered cells that are substituted for the corresponding cells of the received packet, a .DELTA.-CRC remainder that is combined with the CRC remainder included in the received packet to produce a CRC remainder for the altered packet. The station first produces for each altered cell a bit pattern that has zeros in the bit positions in which the bits of the altered cell and the corresponding received cell match and ones in the bit position in which the two cells do not match. The station next encodes the bit patterns in accordance with the CRC code and produces corresponding .DELTA.-CRC values. It then manipulates the .DELTA.-CRC values to produce the .DELTA.-CRC remainder, and combines the .DELTA.-CRC remainder with the CRC remainder in the received packet. The result is the CRC remainder for the altered packet.

Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip.

Abstract: A port aggregation protocol (PAGP) dynamically aggregates redundant links between two neighboring devices in a computer network through the exchange of aggregation protocol data unit (AGPDU) frames between the two devices. Each AGPDU frame contains a unique identifier corresponding to the device sourcing the frame and a port number corresponding to the port through which the frame is forwarded. The exchange of AGPDU frames and the information contained therein allows the neighboring devices to identify those ports corresponding to the redundant links. Each device then dynamically aggregates its ports corresponding to the redundant links into a logical aggregation port (agport) which appears as a single, high-bandwidth port or interface to other processes executing on the device.

Abstract: A multicast engine of a shared-memory switching fabric circuit increases the replication rate of data elements destined for multicast connections within a network switch by manipulating address information relating to those elements. The multicast engine cooperates with other components of the switching fabric circuit to minimize the total buffer requirements of the switch by storing only a single copy of each multicast data element in a location of shared memory. Specifically, the engine has a pipelined architecture that provides a multicasting capability for the switching fabric circuit by replicating only an address pointer to that memory location for each destination of the multicast connection.