Abstract: A computer system is provided for testing components within the system. A closely coupled dual-access fixture is used for electrically interfacing a first side and a second side of a PCB under test. The fixture has a first interface for electrically interfacing the fixture with a first set of test pads on the first side of the PCB under test. The fixture also includes a second interface for electrically interfacing the fixture with a second set of test pads on the side of the PCB under test opposite the first side. Both interfaces include an interface PCB (IPCB). Each IPCB has at least one connector corresponding to a connector on the PCB under test. Each of the connectors on the PCB under test has test pads on the side opposite the connector.

Abstract: A computer system is capable of recovering from a deadlock using communication gateway devices, such as a bridges, which each use a deadlock recovery mechanism. Rather than avoid deadlocks through constant monitoring of the communications path, the bridge allows the deadlock to occur. The recovery mechanisms of the bridges control the resolution of the deadlock. In one embodiment, the recovery mechanism within each bridge causes the local device which controls its bridge to disconnect. Additionally, the bridges terminate their requests for control of each other, thereby breaking the deadlock and allowing communications to resume. In another embodiment, the recovery mechanism within each bridge terminates the bridge's request for control of the other bridge. Additionally, the recovery mechanisms cause the bridges to become idle in accordance with a time delay value. The bridge with the shorter delay becomes active first and takes control of the communication path, thereby breaking the deadlock.

Abstract: A structure and related method for generating phase enable signals for a multi-phase switching power supply with the characteristic that each signal has the same frequency, but each differs in phase relationship. The structure includes a clock circuit coupled to a shift register and clocking the shift register. The shift register has one of its outputs coupled to its shift input signal line. Clocking of the shift register with the clock circuit produces a series of phase enable signals, at the shift register's shift output signal lines, to be coupled to switching phases of a multi-phase switching power supply. The circuit easily adapts to varying number of phases of the multi-phase switching power supply by changing which of the several shift output signals couples back to the shift input signal.

Abstract: A computer graphics system maps textures to displayed anti-aliased images with surfaces defined at oblique angles to the viewer. A circular pixel filter is projected onto a texture map to define an elliptical footprint in that texture map. The elliptical footprint has a major axis. Sample points are determined on a line in the footprint that closely approximates the major axis. These sample points are mapped to levels of detail and locations within a mip-map. Using a space-invariant filter, a texture value is computed for each sample point using data from one or more texture maps within the mip-map. These texture values for the sample points are post-filtered using a Gaussian filter function and summed to produce a final texture value. Blending the final texture with other characteristics of the pixel a produces the pixel data that are displayed on a display screen.

Abstract: A new system for resolving differences in pixel format is disclosed for use in a collaborative software tool. The disclosed system further determines a frequency distribution of color values within pixels forming a bit map of the display of the shared region on the server system. The disclosed system further forms a color ramp responsive to the frequency distribution of color values. The color ramp includes a number of color ramp entries, where each one of the color ramp entries includes an output color value associated with one or more input color values. The color ramp is then transmitted to a client system. The client system converts pixels received from the server system based on the contents of the color ramp. Further in the example embodiment, the client system converts pixels received from the server system using a color conversion table generated based on the color ramp if the pixels in the client system are of true color format.

Abstract: A robotic telepresence system has a user station at a first geographic location and a robot at a second geographic location. The user station is responsive to a user and communicates information to and from the user. The robot is coupled to the user station and provides a three dimensional representation of the user transmitted from the user station. The robot senses and communicates predetermined types of information to the user.

Abstract: A method determines a random permutation of input lines that produced a permuted set of bits in a bitstream. In a source design, the method replaces a logic element whose input lines are permutable with a test function. The source design is processed by a design tool to generate the bitstream including the permuted set of bits. The test function is probed with test values, and the probe results are compared with the permuted set of bits to discover the permutation of the set of bits. The test values can include a message.

Abstract: A computer system that automatically detects and configures an upgrade peripheral controller(s) when present in an expansion slot(s) during the computer system startup, or otherwise, enables and configures an on-board peripheral controller(s). The selection of either a peripheral controller on the computer system motherboard or an upgrade peripheral controller plugged into an expansion slot is automatically determined during startup of the computer system. The logic circuit and software used to accomplish this automatic selection do not degrade the performance of the selected peripheral controller during normal operation of the computer system since non-critical timing direct current (DC) level signals are utilized. No additional logic gates which could cause additional time delays are introduced into critical timing signal paths. No hardwired jumpers are needed nor desired for automatic selection of the desired peripheral controller during startup of the computer system.

Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a network interface, a nonvolatile memory, and a CPU. The network interface may be coupled to a network to receive a “wake-up” data packet, that is, a data packet that includes a predetermined data pattern for which the network interface can be configured to scan. Upon detecting the wake-up data packet, the network interface can initiate a computer boot-up sequence. The CPU begins a boot-up sequence by retrieving a BIOS from the nonvolatile memory. One portion of the boot-up sequence specified by the BIOS includes determining and accessing a series of target boot devices to locate and retrieve an operating system. Preferably, the order of the series of target boot devices (i.e. the “boot order”) is different from a default boot order if the network interface initiated the current boot-up sequence. Otherwise, the default boot order is used.

Abstract: A method of assigning quantization values for use during the compression of images is disclosed. The method includes constructing a non-parametric model during a training phase based on relationships between image characteristics, quantization values, and required bit resources to encode images. The model is built by considering a wide sample of images. The consideration includes determining the temporal and spatial characteristics of the images, compressing the images over a range of quantization values, and recording the resultant required bit resource on a per characterization/quantization level basis. Once built, the model may be used during real time compression by determining the characteristics of the input image and using the allocated resource to find a corresponding match in the non-parametric model. The associated quantization value is then assigned to the input image.

Abstract: A computer system includes a monitor having a universal serial bus (USB) interface for connecting with a base system. Multiple button and LED controls are conveniently placed on a front bezel of the monitor. As the buttons are actuated, commands are passed to the base system via the USB. An on-screen display button causes an application to be launched on the base system for modifying screen attributes stored in a monitor controller in the monitor. A USB controller in the monitor updates the monitor controller via the USB. A multifunction audio dial is toggled by a bezel button between volume, bass and treble functions. The USB controller is also operable to provide a sustain a blinking LED even while the base system is in a sleep mode. LEDs on the front bezel indicate monitor and base system power status.

Abstract: An apparatus, method and system are provided for scanning documents, and creating holographic and panoramic images. The apparatus provides two sets of prisms, one set of which is made of electro-optical material. The prisms are arranged in alternating rows to form a sheet. The prism sheet can be laid fiat or rolled into a cylinder. A sequencer is used to activate individual electro-optical prisms so that the image is reflected into the sheet. A second prism is used to reflect the image into an image receptor such as a camera. By sequentially activating the electro-optical prisms, successive image portions of an object or objects can be presented to the image receptor. If the image receptor accepts digital input, the sequential images can be post-processed in a microprocessor to create a holographic or panoramic image. Similarly, images of documents can also be scanned and the images received can be digitized for processing, storage and/or transmission.

Abstract: A desktop computer system is provided with a semi-mobile CPU unit having a portable computer form factor to thereby substantially reduce the desktop area required for the CPU unit. The CPU unit utilizes portable computer internal components, but is constructed without an internal battery pack or power conversion system, and without an integral display, keyboard or pointing device. A recessed support bar is exteriorly carried by an end wall of the CPU unit housing and may be pivoted outwardly therefrom to form a bracing base structure facilitating the repositioning of the CPU unit from a horizontal desktop orientation to a vertical tower orientation.

Abstract: A database query compiler and compilation method has special facilities for compiling a query that includes a Rows Since sequence function, Rows Since (search condition). A query normalizer includes a Rows Since function normalizer for normalizing the Rows Since sequence function. The Rows Since function normalizer parses the search condition of the Rows Since function to identify each reference to information from a previously access row and converts each such identified reference into an Offset sequence function, Offset(argument, index). The argument of the Offset sequence function is a specified function of the identified information from a previously accessed row of the table. The previously accessed row has a position that is index rows before the current row referenced by the cursor for the table. The query compiler places the resulting normalized search condition in a search loop that traverses successively earlier rows in the table until it finds a row that satisfies the search condition.

Abstract: A power management system for a converged functionality apparatus enables primary control to be effected through an actuating mechanism. In general operation, the actuating mechanism switches between “on” and “suspended” states. The power management system includes various defaults, memories, and priority setting schemes that enable fully integrated, but wholly intelligent, operation of the converged functionality apparatus.

Abstract: A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.

Abstract: A modem which is separated into two circuit boards. One board contains the modem engine, while the second board contains the codec and the DAA components. The two boards are connected using only properly isolated digital signals so that the modem engine board does not require certification, only the codec/DAA board requiring certification. The codec/DAA board is contained in a housing to provide proper high voltage protection.

Abstract: A transaction processing system, including multiple processor units communicatively interconnected, manages information collection by employing a distributed transaction management facility to track and make consistent changes. When each transaction is started, a data structure is created that maintains information concerning the transaction. Included in the data structure is the identity of all processor units having resources involved in the transaction. Should a processor unit fail, and the transaction management facility is notified of that failure, the data structures of all pending transactions will be examined to see if the failed processor unit had a resource that was a participant in the corresponding transaction. If so, the transaction management facility can then make a decision as to whether or not to abort the transaction.

Abstract: A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be used for difficult to test situations such as embedded CAM or other memory types. There are no external memory read operations to determine the contents of a memory location, so little additional circuitry or overhead, such as separate read ports, is required on the embedded memory for implementation of the BIST. Only a number generator, a shift register and an OR gate with inputs from each of the CAM word match lines are added to the circuit in which the memory is embedded. The test uses a set of unique data patterns, each one spaced from the others by two bit locations, a walking inversion test, and a complement and reverse pattern test to determine what type of error and the error location.

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.