Abstract: The invention is a method and apparatus for the thermal management of computers. The method features determining a temperature of a predetermined location in the computer, reading indirect inputs of the computer, determining desired states of cooling options based on the temperature and the indirect inputs, and placing the cooling options in their desired states. To determine the desired states of the cooling options, an index is formed based on the indirect inputs; and the index indicates to which of a plurality of tables of desired states of the cooling options to refer. Alternatively, the desired states of the cooling options are determined by adjusting the value of the temperature input based on the indirect inputs; the desired states of the cooling options also are dependent on the adjusted value of the measured temperature.

Abstract: Apparatus is provided for a heat transfer assembly for direct attachment to a high heat generating chip, which assembly includes a pump, air side heat exchanger mounted adjacent to a fan and a heat transfer plate which is attached to the high heat generating component for dissipating heat from such component under operating conditions. In another embodiment, apparatus is provided for dissipating heat from a hard disk drive including a U-shaped heat exchange clip resiliently mounted on opposite surfaces of a hard disk drive. In another embodiment, apparatus for dissipating heat from a hard disk drive includes a generally rectangular plate for mounting on the top or bottom of the hard disk drive. And, in another embodiment, apparatus is provided transferring heat from a vertical array of hard disk drives, which apparatus includes one or more panels interposed between adjacent vertically disposed hard disk drives.

Abstract: A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed by the memory sub-system. The recorded states from a subset of the selected transactions are statistically analyzed to estimate statistics of the memory transactions.

Abstract: A portable audio player stores a large amount of compressed audio data on an internal disk drive, and loads a portion of this into an internal random access memory (RAM) which requires less power and less time to access. The audio player plays the data stored in RAM and monitors the amount of unplayed data. When the amount of unplayed data falls below a threshold, additional data is copied from the disk drive into RAM. Because the time necessary to copy a block of data from the disk drive to RAM is much less than the amount of time it takes to play the same block of audio data from RAM, this approach minimizes the amount of time that the disk drive must be operated, and thus minimizes the amount of power consumed by the system.

Abstract: A computer graphics system renders an image on a display device using improved pre-filtering techniques that minimize aliasing artifacts in the image, particularly at the endpoints of lines. To anti-alias the image, a plurality of edges are placed near a line in the image. An edge function represents the edge. This edge function is multiplied by a scale factor to produce a distance function. This scale factor is the reciprocal of the Euclidean length of the line. The distance function is evaluated to determine the distance of selected pixels from each edge in units of pixels. These distances determine the intensity value for each selected pixel. Pixels on or beyond an edge, with respect to the line, are given a minimum intensity value; pixels inside all edges are given intensity values corresponding to their distances from the edge. An intensity function describing a relationship between pixel distances from the edges and their corresponding intensity values is developed.

Abstract: A method generates a one-dimensional dither array having a predetermined number of dither values stored at addresses of the array includes the steps of generating a choice size vector and a choice vector. Initializing an address of the dither array, a dither value, and a counter for indexing the choice size vector and the choice vector to zero. Determining if the dither value is equal to the size of the dither array, and terminating if true, otherwise if false continuing with assigning a step a value that is equal to the size of the dither array divided by a current value of the indexed choice size vector, and assigning an offset a value that is equal to the rounded-down integer value of the step divided by two. Assigning the address, modulus the step, equal to the address, plus the offset, plus the current value of the indexed choice vector multiplied by the step.

Abstract: A method for defining the elliptic curve for purposes of elliptic curve encryption using biometrics such as a fingerprint to define the elliptic curve equation's coefficients.

Abstract: A method and device for enhancing the sharpness of a video image. The luminance signal portion of a television signal is boosted in its upper frequency range, e.g., between about 2.0 MHz and about 4.25 MHz. This enhancement of the luminance signal accentuates the transitions between the high brightness levels and low brightness levels of the luminance signal. The resulting video image appears much sharper because this quicker transition reduces the amount of signal carrying intermediate brightness information.

Abstract: Information is sent on a pair of conductors by sending some of the information by driving the pair of conductors in accordance with a primary signaling character set having two distinct information-carrying characters, and sending other information by driving the pair of conductors in accordance with a third distinct information-carrying character represented by a predefined state of the pair of conductors.

Abstract: A computer system having a highly parallel system architecture with multiple central processing units, multiple core logic chipsets and pooled system memory is provided with one or more AGP ports capable of connection to AGP devices. A memory manager is provided within the operating system for allocating pooled memory resources without regard to the location of that memory. A method is presented for dynamically allocating memory for the AGP device that is located on the same core logic chipset to which the AGP device is connected. By allocating local memory instead of allocating memory on remote core logic units, the AGP device can access the needed memory quickly without memory transmissions along the host bus, thereby increasing overall performance of the computer system.

Abstract: In a digital signal processing system, such as a computer system, an apparatus for communicating digital signals in a plurality of operating domains. The first domain has first timing and control signals synchronized to a first clock. In response to an event, the apparatus dynamically transitions the operation of the synchronous memory to a second domain having second timing and control signals synchronized to a second clock. The first timing and control signals being different in frequency, shape, and protocol than the second timing and control signals. The first clock can be a processor clock to synchronize communication of address and data signals with a processor, and the second clock can be a system clock to synchronize communication of address and data signals with an asynchronous data processing device such as random access memory.

Abstract: An efficient method is presented for automatically verifying test patterns devised to detect speed critical faults in electrical circuits, with minimal human intervention. The method provides a controlled momentary inversion of a logic value at a control point within the circuit being tested or simulated, and then checks the measured or simulated circuit's output value. If the momentary logic inversion causes an inverted logic output, then the test pattern under evaluation has been determined to be capable of detecting circuits that have failures due to speed critical problems. With such an arrangement it is possible to determine whether specific test patterns will accurately measure the performance of circuit paths that have potential operating speed related problems.

Abstract: A cable management system for organizing and controlling cables extending from an electronic device while providing substantially unimpeded device access, substantially unrestricted cable movement and substantially unrestricted air flow into and out of the device. The system attaches to a secure structure and is capable of boxing out from the structure to allow access to service a device positioned within the secure structure. The cable management system includes at least three cable arms of rigid material, a coupling member attached between each adjacent pair of the at least three cable arms, where the coupling member provides movement between each of the adjacent pairs of cable arms.

Abstract: The invention is a system for time shifting live, streamed video and/or audio distributed via a global computer network, e.g., the Internet. The invention is preferably implemented as client-server software, with the possibility of both the client and the server running on the same PC. Alternatively, the system software may be embedded within a digital VCR information appliance, giving the system the ability to time shift and display Internet content as well as broadcast video content received via cable or satellite.

Abstract: A method of limiting, in a digital processor, low-priority utilization of a resource in favor of high-priority utilization of the resource comprises determining a value predictive of high-priority utilization of the resource. Low-priority utilization of the resource is inhibited if the determined predictive value is greater than a threshold. On the other hand, if the predictive value is less than or equal to the threshold, then low-priority utilization of the resource is allowed. In a preferred embodiment, the predictive value is derived by counting the number of actual high-priority utilizations of the resource out of the last N opportunities in which the resource could have been utilized for a high-priority need. Preferably, recent utilizations are given more weight than others. In a preferred embodiment, the resource comprises one of main memory, instruction cache memory, or data cache memory.

Abstract: A method and computer system according to the disclosed invention allows the pre-installation of a software application without a license key. The computer system installs a software application and provides a prompt for a license key. The license key is stored in a registry. If the license key is not entered, the computer system installs the software application and installs disabling code. At startup, the code is executed if installed, providing a prompt for a license key. If the proper license key is entered, the computer system stores the key in a registry and uninstalls the disabling code, allowing installation of the software application. If an improper key is entered, the computer system allows the key to be reentered.

Abstract: The invention a customer information control system (CICS) application programming interface (API), with global and local system and file control functions, in a loosely coupled data processing system environment. In accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed to a method, system and computer readable medium for the local system and files control (hereafter collectively referred to as the “invention”). In particular, the invention includes implementing a loosely coupled CICS region in a data processing environment, the loosely coupled CICS region includes at least two of a plurality of machines and their respective address spaces. The invention further includes allocating a flat segment in the address space of the at least two machines. The invention additionally includes providing a keeper in the address space of each of the at least two machines, one of the keepers being designated as a master keeper.

Abstract: A method for permitting software optimization tools, software instrumenting tools and other analysis tools to re-write executables having mixed instructions and data uses a data structure having an entry for each multi-bit word in an executable file. Each entry of the data structure includes a number of flags that are set to identify the type of the multi-bit word in the associated line of the executable file. The types include instruction, data and unclassified. Each entry also includes a flag that indicates that the multi-bit word should not be optimized and a flag indicating that the multi-bit word is a problem branch. The no-optimize and problem branch flags may be used to identify multi-bit words that may be either branch instructions or data, and to ensure that such multi-bit words are not affected by optimization or other rewriting of the executable. In addition, a problem fall through flag is provided to maintain program flow for possible fall through code segments.

Abstract: A system and method are provided for performing modulo multiplication of two numbers N bits long with a modulus of 2N+1, where the resulting modulus is determined without a need to perform successive reductions. Without a need to perform successive reductions, a hardware implementation does not require a divider circuit.

Abstract: A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a cycle to memory is initiated on the PCI or AGP bus by a peripheral device, a snoop control circuit of the bus bridge arbitrates for the processor bus to initiate a snoop cycle which corresponds to the line being accessed by the peripheral device. In addition to performing a snoop for the current line being accessed, the snoop control circuit further advantageously runs a speculative snoop cycle for the next sequential line. By performing a speculative snoop cycle on the CPU bus to the next line address, latencies associated with subsequent accesses to memory by the peripheral device may be reduced if the device performs a subsequent sequential access. Furthermore, since the bus bridge performs multiple snoop cycles per arbitration cycle (e.g.