Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus.

Abstract: A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed.

Abstract: A symmetrical processing system includes a number of processor units sharing a memory element. At least a portion of the memory element is partitioned so that separate memory partitions are made exclusively available to some if not all the processor units.

Abstract: A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.

Abstract: A monitor function is implemented to monitor and control service processes and other system entities that perform tasks on a distributed network. The monitor function tracks the demise and instantiation of processes and entities that either export or import instrumentation. Any service process or other system entity (driver, interrupt handler, system library procedure) can export instruments (indicators, controls, testpoints). Instrument updates are propagated automatically if they are significant. The importing process conveys the information to a management system so that a human operator, or automated system, can observe and control the operation of the network service. One aspect of the invention uses a backup exporter to take over the processing of an exporter that has become nonfunctional. Another aspect of the invention determines when a CPU has gone down and acts accordingly to identify service processes that were associated with an exporter in the down CPU.

Abstract: A computer system having automatic speaker detection circuitry is disclosed. The typical computer system includes a central processing unit, a data input device, and a sound card. Further, there is an audio amplifier, as well as an automatic detection and selection circuit that may be within the sound card or the audio amplifier or just part of the computer system as a whole. This automatic detection selection device is able to determine an impedance load of an output device attached to the computer system, namely, a speaker system, and is able to disable the audio amplifier within the computer system upon determining the impedance load and matching that impedance load against a selected value indicating that no amplification of the signal is required for the output device. Further, an audio sound equalizer is part of the system and can be bypassed in the same manner that the audio amplifier is, namely, that particular impedance load is measured indicating that no equalization is necessary.

Abstract: A system for timing intervals in a computer. The system provides an interval timing service for processes running in a computer system. The timing service supports a potentially large number of interval timers by using “timing wheels” that “turn” at different periods. The time base for the fastest turning wheel can be an interrupt event or some other hardware or software control.

Abstract: An image generator computes a set of light sample points, wherein each light sample point is a point on a light source from a geometric model, and an irradiance image is computed for each light sample point, wherein an irradiance image is a view-dependent image taken with the light sample point being the view point and the light source for the irradiance image. From the irradiance images, the image generator creates an irradiance texture for each object in a set of objects being considered the scene and the image generator renders the image of the objects in the set of objects with each object's coloring determined, at least in part, from the object's irradiance texture. Depending on performance requirements, one or more operation of the image generator is parallelized.

Abstract: A forced flow of cooling air through a computer housing is created during operation of a specially designed data storage disc drive structure operatively disposed in the housing. The drive, which is illustratively a CD ROM drive, has a bladed carrying structure which supports a compact disc and is rotationally driven with the supported disc. Driven rotation of the bladed carrying structure creates the forced flow of cooling air within the housing without requiring additional space for a separate cooling fan therein. In two illustrated embodiments of the bladed carrying structure the created cooling air flow is generally parallel to the rotational axis of the compact disc, and in a third embodiment of the bladed carrying structure the created cooling air flow is generally transverse to the rotational axis.

Abstract: A storage system capable of selectively presenting logical units to one or more host computing systems. The storage system comprises one or more persistent storage devices arranged as logical units; an array controller controlling and coordinating the operations of the persistent storage devices; a memory accessible by the array controller; and a configuration table stored in the memory, the configuration table containing one or more entries governing the interactions between the logical units and the one or more host computing systems.

Abstract: An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/0 operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller.

Abstract: The present invention relates to a monitor base that comprises a serial bus hub having a plurality of ports connected to the hub for interface with a plurality of peripheral devices. With the ports located on the monitor base hub, a computer system's peripheral devices, i.e., keyboard, mouse, printer, scanner, video camera, etc., are connected to the monitor base hub instead of on the rear of the central processing unit.

Abstract: A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode.

Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a user input device, a nonvolatile memory, a network interface, a boot trigger, and a CPU. The CPU is coupled to the user input device to detect a predetermined key press, coupled to the boot trigger to detect the assertion of a system reset signal, and coupled to the nonvolatile memory to retrieve a system BIOS in response to assertion of the system reset signal. The CPU executes the BIOS to initialize the computer system, and as part of the system initialization, the CPU determines a first target boot-up device. Preferably if the predetermined key has been pressed during the system initialization, the CPU alters the default boot order to select the network interface as the first target boot up device. The network interface is configurable to retrieve an operating system from a network device for the CPU to execute.

Abstract: A lever system deploys a pinion gear that engages a pinion gear receiving portion. A handle is attached to the pinion gear to rotate the pinion gear between a retain position and a release position. The pinion gear receiving portion is attached to a first object and the pinion gear is pivotably mounted to a second object that may be moved with respect to the first object. The design of the pinion gear receiving portion and the pinion gear ensure linear travel of the second object as the pinion gear is rotated between the retain position and the release position. Additionally, the pinion gear and the receiving portion include contours that prevent relative linear motion in all directions.

Abstract: An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes on very thin gate oxide transistors are greatly improved, resulting in improved gate threshold voltage control and improved transistor electrical properties, without loss of the benefit of self aligned source and drain electrodes available with polysilicon gates. Dual metal gate electrodes are also disclosed and exhibit improved CMOS transistor function compared to polysilicon gates, resulting in better and more controlled transistor properties. Thus the metal Damascene gate process results in faster and more consistent MOS and CMOS transistors and improved IC fabrication.

Abstract: The invention recognizes that a probability density function for fitting a model to a complex set of data often has multiple modes, each mode representing a reasonably probable state of the model when compared with the data. Particularly, sequential data such as are collected from detection of moving objects in three dimensional space are placed into data frames. Also, a single frame of data may require analysis by a sequence of analysis operations. Computation of the probability density function of the model state involves two main stages: (1) state prediction, in which the prior probability distribution is generated from information known prior to the availability of the data, and (2) state update, in which the posterior probability distribution is formed by updating the prior distribution with information obtained from observing the data. In particular this information obtained purely from data observations can also be expressed as a probability density function, known as the likelihood function.

Abstract: When a source program containing annotations is processed by a user-selected tool, the annotations in the source program are detected by a lexer and passed to an annotation processor corresponding to the selected tool. The system contains a number of annotation processors and a number of program processing tools, and the annotation processor to which the annotations are passed is selected based upon the user-selected tool. The selected annotation processor converts annotations compatible with the user-selected tool into annotation tokens and returns the annotation tokens to the lexer. The lexer generates tokens based upon the programming-language statements in the source program, and passes both the tokens and annotation tokens to a parser. The parser, in turn, assembles the tokens and annotation tokens into an abstract syntax tree, which is then passed to the user-selected tool for further processing.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity, which minimizes the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: A method implemented according to the invention allows a user to specify with particularity hierarchical structures such as computer hardware and peripheral equipment in such a way that it simplifies the storing, retrieving, and manipulation of the information.