Abstract: The invention provides a method for acquiring a lock in a network of processors with globally ordered remote-writes. A process requesting a lock changes an associated ticket number from zero to one. Next, the process determines if every other process attempting to acquire the lock has a ticket number of zero. If true, the request for the lock is immediately granted. Otherwise, if false, the process changes its ticket number to a value greater than that of every other process, and the process waits until its ticket number is the lowest non-zero ticket number, in which case the lock is granted with mutual exclusion.

Abstract: A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

Abstract: A computer system according to the present invention implements a self-modifying “fail-safe” password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.

Abstract: A technique for providing hardware interrupt simulation using the interprocessor interrupt mechanism of the local Advanced Programmable Interrupt Controller (APIC) on a Symmetric Multiprocessor (SMP) System running Windows NT is disclosed. The interrupt simulation is performed by first determining the Interrupt Request (IRQ) vector that is associated with a particular system device driver. In the case of devices being emulated, the determination of the IRQ vector is done by intercepting the messages from the interrupt invoking procedure. The IRQ vector provides a pointer to the device driver's Interrupt Service Routine (ISR). After the device driver's ISR is connected to the appropriate interrupt vector entry in the Interrupt Descriptor Table (IDT), the vector number is combined with the local APIC constant and followed by a 32-bit write operation into the lower part of the Interrupt Control Register (ICRL) of the local APIC.

Abstract: A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.

Abstract: A memory interface controller employs a DATUM multiplier within a destination address to perform DATUM RAID operations. If destination data is in an XOR memory address space, then the multiplier can indicate to multiply source data by the multiplier and XOR that resulting data with the destination data. The DATUM multiplier can be read in response to detection of a memory command. The multiplier alternatively can be used in connection with an input/output bus write command to write source data from the input/output address space to an XOR memory address space. In response to such a write command, the input/output bus data in the input/output address space is multiplied by the multiplier; that resulting data is XORed with the destination data in the XOR memory address space. The multiplier in this case can be within an input/output bus address associated within the input/output bus data.

Abstract: A multi-user bus is divided into a number of bus portions, one for each user. Each bus portion is coupled, at one end, to one of the multiple users and through an impedance matching network to the other bus portions in a star configuration. The disclosed embodiment teaches various resistive impedance matching networks.

Abstract: A technique for reliable passage of handshaking information between a cellular modem and a land modem. Instead of bare transmission over a voice channel connection highly susceptible to signal fading and dropout, the initial modem handshaking exchange is instead FSK-encoded and broadcast using a network data signalling methodology already used to reliably pass signalling information between the base and registered mobiles. Automatic retransmission request signalling and transmission redundancy may be implemented to insure successful receipt at the receiving end of the radio link. Once received and verified, handshaking information is decoded and delivered to the destination modem in the appropriate format along cleaner fixed pathways. Reliable handshaking operations are contemplated whether the destination modem is a cellular modem registered in auto-answer mode (land-originated data call), or a land modem (mobile-originated data call).

Abstract: A method and apparatus are provided for improving the data hold timing requirement of the sense amplifier by coupling a pass-gate to its data input ports. Each pass-gate receives a logic level that has developed on an input data signal. When the data is valid, a control signal is asserted that causes the pass-gate to latch the logic level at the input of the sense amplifier. While that logic level is latched, the sense amplifier can generate a corresponding latched output signal and the data signal can transition to a new logic level. Therefore, the pass-gate maintains the logic level at the input of the sense amplifier for the duration of the data hold timing requirement. The pass-gate can be a level-sensitive latch that latches said first logic level in response to the assertion level of the control signal. It includes a first transistor having a drain terminal connected to the data signal, a source terminal connected to the sense amplifier and a gate terminal connected to the control signal.

Abstract: A computer microprocessor has a housing portion with a recess formed in a top side wall thereof, and a die portion inset within the recess. Operating heat from the die is removed by heat dissipation apparatus which automatically adapts to variations in the microprocessor bond line thickness and includes a sheet metal EMI shield wall overlying the microprocessor and having a condensing end portion of a thermosyphoning heat pipe secured to its bottom side, with an evaporating end portion of the heat pipe overlying the die recess and being resiliently deflectable toward a phase change thermal pad mounted on the top side of the die and inset into the housing die recess. A metal heat sink member is rotatably mounted on the heat pipe evaporating end portion and has a flat bottom side and an arcuate top side.

Abstract: The SQL compiler and SQL executor in a database management system are extended to process queries requiring streaming mode processing of data stored in a table. A scan operator performs table access functions during execution of the streaming mode query. The scan operator first performs an initial scan to access rows in a specified database table, and then performs a delta scan to access new rows added to the table, as well as rows modified by other queries. The scan operator continues to process new data added to the table until the initiating user or application closes the associated cursor. A set of data structures are provided to keep track of active scan operators, including a session control block that includes fields for keeping track of whether the scan operator is performing an initial scan or a delta scan. The session control block also includes, for streaming mode scan operators, a delta scan list of new and modified rows to be processed in the delta scan.

Abstract: A portable computer docking base has incorporated therein a thermoelectric cooling system used to provide auxiliary operating heat dissipation for a portable notebook computer operatively docked to the base. The cooling system includes a thermoelectric (Peltier effect) heat pump unit disposed within the docking base housing and having opposite hot and cold sides. A finned heat sink member is secured to the hot side of the assembly and positioned in the path of fan-generated cooling air, and a heat slug member is secured to the cold side of the assembly and projects outwardly through an exterior wall of the docking base housing into its computer receiving area. When the computer is placed in the receiving area and docked, the cooling system heat slug member is brought into heat conductive contact with a similar heat slug member carried within the computer and thermally coupled to its microprocessor.

Abstract: A computer may be easily user re-configured between desktop and tower housing orientations, with the computer's front side drive units being horizontally disposed in each orientation, using specially designed drive unit support and a reconfigurable front bezel. A square opening is formed in the front exterior wall of the housing, and the support apparatus includes spaced apart channel structures extending inwardly into the housing from the four sides of the wall opening, with opposing pairs of the channel structures being adapted to slidably receive corresponding projections on opposite side edge portions of the drive units. In this manner, each front side drive unit can be supported at the opening in a first orientation in which the drive unit will be horizontally oriented with the computer in a desktop orientation, or a second orientation in which the drive unit will be horizontally oriented with the computer in a tower orientation.

Abstract: A system operable with a Digital Versatile/Video Disc source, provided with a scheme for preferably automatically pausing the playback of a DVD title when a user indicates that another activity is to be engaged. By automatically pausing the title playback, computational load on a processor subsystem associated with the system is minimized while graceful management of the additional video sources is effected. When the user switches to experiencing the DVD source as the primary source, the playback of the title is preferably automatically resumed.

Abstract: An apparatus and method to force the computer system to boot from the boot block. During a computer system power-up and initialization, the computer system determines if the escape key is pressed. If so, the computer system will boot from the code in the boot block, proceeding as if the flash ROM is corrupted. This forces the computer system to boot from the boot block even though the system determines that the flash ROM is not corrupt, allowing the user to flash a ROM at the user's discretion.

Abstract: A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

Abstract: A system for timing intervals in a computer. The system provides an interval timing service for processes running in a computer system. The timing service supports a potentially large number of interval timers by using “timing wheels” that “turn” at different periods. The time base for the fastest turning wheel can be an interrupt event or some other hardware or software control.