Abstract: A docking system, including a portable computer and a docking unit, operates by latching the portable computer to the docking unit. A docking bay arrangement is used so that the portable computer's keyboard is accessible and usable by the user. A latch control system, which is controlled from the portable computer, provides security by preventing removal of the portable computer from the docking unit by unauthorized persons. This prevents theft, since the docking unit in turn is secured to the work area by a cable system.

Abstract: A method and apparatus of controlling the brightness level of an LCD display. The brightness of a display having two light bulbs may be controlled by illuminating only one bulb to provide a relatively low brightness level or by illuminating both bulbs to provide a relatively high brightness level. This method and apparatus may be particularly useful in AC/DC powered devices, as a single bulb may be lit when the device is operating on DC power to conserve battery power, and both bulbs may be lit when the device is operating on AC power to provide enhanced brightness.

Abstract: A new system and method for sharing graphical display information in a collaborative tool is disclosed which samples graphics display information regarding a shared display region on a server system. The disclosed system updates client systems regarding changes in the shared display region responsive to detection of a change in the shared display region contents. The disclosed system further modifies a polling rate used to sample the graphical display information on the server responsive to the frequency of changes to the shared display region. Specifically, in an example embodiment the disclosed system shares a display region among a plurality of users by selecting a first bit map from a series of bit maps used to display the shared display region on a server system. The server system then transmits said first bit map to a client system. The server system periodically selects a subsequent bit map from the series of bit maps at a polling rate.

Abstract: A portable computer system with planar speakers. The planar speakers are fabricated with a coplanar array of small, low cost, durable, electromagnetic speaker elements mounted on a panel. The planar speakers can be attached to the lid of the computer system. The planar speakers can slide into a compartment in the lid of the computer system when not in use and slide out of the compartment for use with greater physical separation than that of built-in speakers. Alternatively, the planar speakers are attached to the lid via a hinge and folded against the lid when not in use. The planar speakers are folded outward extending the planar speakers beyond the lid for use with greater physical separation than that of built-in speakers. The planar speakers can be detachable from the remainder of the computer system for greater spacing and variable positioning of the planar speakers for improved stereo sound reproduction.

Abstract: A computerized method is provided for connecting a remote computer to a local area network (LAN) via the Internet. An identification is sent to a gateway of a local area network using a publicly accessible communications network, either by a user or by a modem of the remote computer. The gateway uses the sent identification to index a database and read a profile record specifying an Internet Service Provider. The gateway makes a request of the specified Internet Service Provider to assign an IP address. Upon receiving the assigned IP address, the gateway sends a mail message including the Internet address to a mailbox at a mailbox address specified in the indexed profile record. The user of the remote computer reads the mail message to obtain the IP address, and the dynamically assigned IP address can then be used to connect the remote computer to a local area network (LAN) via the Internet.

Abstract: An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a currently processed instruction is sampled when the currently processed instruction belongs to the identified class of instructions. A shift register stores a predetermined number of entries storing selected state information, the shift register is simultaneously sampled along with additional state information about the instruction being executed at the time of sampling.

Abstract: A method and apparatus for generating test data is presented. A data generator produces data using element specifications contained in an input script. The data generator includes a specification analyzer and data synthesizer. The data generator produces the data that includes varied combinations of the element specification generated in a particular order. Both the combination and the particular order in the generated sequence may vary in accordance with a specified method of data generation. Three methods of data generation--carry-out method, grey code method, and all-change method--are described.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.

Abstract: A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.

Abstract: A proxy system that offers connection services and acceleration services is disclosed. The acceleration services provide for accelerated delivery of content to requestors (e.g., clients) while guaranteeing a minimum level of service (for content delivery) to the requestors. The acceleration services are facilitated by improved techniques for rapid and efficient delivery of objects from a network (e.g., the Internet) to users. The improved techniques can be utilized in a variety of apparatuses, including a proxy having an acceleration apparatus (e.g., an acceleration server). The acceleration apparatus manages and monitors its utilization of processing resources so that performance of the proxy system can during worst case conditions guarantee a minimum level of service (for content delivery) to the requestors. The proxy system is also well suited for being scaled to provide additional processing resources.

Abstract: A computer system including a programmable bridge logic device to disable various peripheral device functions is disclosed. The bridge logic device preferably includes an address decoder and one or more peripheral bus controllers. The address decoder preferably includes a configuration disable unit comprising one or more programmable status bits. Each status bit is associated with a particular peripheral device function, such as a IDE or USB functions. When a status bit is set, configuration cycles to the function corresponding to that bit are disabled. In one aspect of the invention, the computer system comprises a laptop computer that can be docked to an expansion base. The laptop and the expansion base may duplicate one or more functions. When docked, the status bit in the bridge device associated with a function also provided in the expansion base is set disabling the duplicate function in the laptop in favor of the function in the expansion base.

Abstract: A method for providing a memory model for simulation which includes the steps of allocating from memory a block of contiguous memory cells, storing a model of memory corresponding to a memory device in the memory, associating the stored model of memory to a corresponding one of the memory cells of the block of contiguous memory cells and, storing a location of the associated one of the memory cells within the model of memory.

Abstract: A computer may have a management bus installed, where the management bus is coupled to sensors which monitor status of components of the computer. The management bus may also be coupled to a management bus processor, where the management bus processor receives status information from the management bus concerning status of components of the computer. An interface between the management bus and the network subsystem permits transmission of an error message in the event that the computer has a failure which inactivates the system CPU, the system bus, the system memory, or the system power supply.

Abstract: Entries are cached in a function cache by statically assigning a primary key to each cache entry, and first grouping entries having identical primary keys, and dynamically assigning a secondary key to each cache entry, and then second grouping entries in each primary key group into sub-groups according to their secondary keys. The function cache is first accessed with a particular primary key to get the primary key group. Second, the primary key group is accessed with a particular secondary key to get a sub-group, and third, the sub-group is accessed with the same particular secondary key to get a matching cache entry.

Abstract: A run-time security methodology and apparatus for supporting complete access to the security features of a network computer by a network administrator. In a network computer according to the invention, various resources are secured by a security device. The resources are accessible by a computer user with knowledge of one or more user passwords stored in the security device. An administrator password is also stored in the security device. In addition to control access to specified resources, the administrator password also functions as a surrogate for the other passwords stored in the security device. An administrator password implemented according to the invention thereby allows a network administrator to remotely override any activated user security settings and receive complete access to a secured network computer.

Abstract: A computer system with an Intelligent Input/Output architecture having a scheme for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, a first input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions. A masking module is provided for rendering at least a portion of the plurality of peripheral devices hidden from the host operating system and host processors. The masking module is configured upon system initialization and the contents of the module are used in blocking IDSEL signals associated with the portion of peripheral devices subordinated to an I/O processor.

Abstract: A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.

Abstract: A computerized method is provided for generating passwords for password controlled access points. Provided are a master password, an access password, and a user name. The master password, the service name, and the user name are combined using an irreversible function to generate a unique password. The function can be a one-way hash function. The combining can be performed by a browser of a client computer. A similar combining can also be used to generate a user name from the master password and the user's real name.

Abstract: A security device and methodology that prevents unauthorized access to general purpose I/O pins in a computer system. In a system according to the invention, secure general purpose I/O pins are utilized as enable signals for data transfer devices such as Universal Serial Port (USB) ports. In one embodiment of the invention, access to the secure general purpose I/O pins is governed by an administrator password that is protected by a memory slot in a security device. When an administrator (or other authorized user) desires access to the general purpose I/O register that controls the secure general purpose I/O pins, the administrator enters the administrator password. If the password is correct, the relevant slot of the security device is unlocked, thereby permitting completion of write cycles to the secure general purpose I/O register. If a write cycle to the secure general purpose I/O register is attempted while the relevant slot in the security device is locked, the write cycle is ignored.