Abstract: A multi-boot apparatus allows a portable computer to boot from a predetermined list of bootable data storage devices, even if the data storage devices have been relocated during operation. The computer system has a hard disk bay and multi-bay for accepting one or more data storage devices and/or battery packs. During initialization, the invention retrieves a previously entered IPL sequence from a configuration setup table stored in the nonvolatile RAM of the portable computer. Next, the invention queries each bay and determines the device connected to each bay, including the data storage device and the battery pack, if one is present. The invention then determines if a remapping of the data storage drives is necessary to ensure that the device at the beginning of the IPL order is the first drive in the BIOS boot sequence. If so, the invention remaps the drives such that the device is at the first drive in the BIOS boot sequence.

Abstract: A computer docking station has a disk drive module incorporated therein which is capable of operatively receiving a disk drive therein. The disk drive module is also capable of being operatively installed within a desktop computer or other enclosure having a half-height bay therein. Security features of the docking station include preventing access by unauthorized persons to the disk drive, and preventing ejection of the disk drive from the disk drive module. Additionally, multiple disk drive modules may be cooperatively linked in the docking station so that the security features relating to each of the disk drive modules may be simultaneously actuated.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A system for recovery of process relationships following node failure within a computer cluster is provided. For relationship recovery, each node maintains set of care relationships. Each relationship is of the form carer cares about care target. Care relationships describe process relations such as parent-child or group leader-group member. Care relationships are stored at the origin node of their care targets. Following node failure, a surrogate origin node is selected. The surviving nodes then cooperate to rebuild vproc structures and care relationships for the processes that originated at the failed node at the surrogate origin node. The surviving nodes then determine which of their own care targets were terminated by the node failure. For each terminated care targets, notifications are sent to the appropriate carers. This allows surviving processes to correctly recover from severed process relationships.

Abstract: A computer system is selectively booted into an advanced configuration and power interface (ACPI) mode or a non-ACPI mode during computer system start-up, depending upon the status of a user specified flag. The instructions and data needed to boot the computer system into ACPI mode can be stored in a memory in a format not visible to the computer system operating system. A user can specify the desired boot mode through a user set-up routine.

Abstract: An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

Abstract: A computing system performs non-restoring division. Quotient selection logic selects quotient digits that are used to produce a final quotient. The quotient digits are selected according to a predetermined relationship among certain bits of the divisor and the partial remainder. Only non-zero quotient digits are selected. A quotient accumulator combines each selected quotient digit with a current partial quotient concurrently while each quotient digit is selected. The quotient digits are selected and combined until the final quotient is produced.

Abstract: A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable ROM (PROM) through the serial PROM interface of the controller. The random-access memory controller randomly accesses the BIOS code in the serial PROM during power-up of the computer system in response to read requests from the CPU. If the memory controller cannot immediately process the read requests from the CPU, the controller creates wait states for the CPU. The auto-configuring memory controller sequentially accesses the entire BIOS code in the serial PROM during power-up and prior to the running of the CPU, and copies it to a portion of base memory eliminating random accesses to the PROM.

Abstract: A thermal management technique for a computer system having a thermal device and a timer includes establishing a thermal window having low and high temperature thresholds, causing the timer to generate an interrupt at a specified interval, and processing the interrupt. During interrupt processing, if the thermal device indicates the current temperature is outside the established thermal window, the thermal window is adjusted by resetting the low and high temperature thresholds to bracket the current temperature and then notifying the operating system that a thermal event has occurred.

Abstract: In a computerized method for collecting speech data, Web pages of client computers connected to the Internet are enabled to acquire speech signal and information characterizing the speech. The addresses of the enabled Web pages are stored in a list in a memory of a Web server computer. Based on predetermined criteria and the list, some of the enabled client computers are selected to acquire the speech signal and information. The acquired speech signal and information are transmitted to the server computer to generate, train, and evaluate acoustic-phonetic models.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, and the operating system driver software need not even have its input and output instructions replaced. Instead, debug registers are provided as breakpoints whenever an input/output instruction is executed to the I/O port range at which the UART would normally appear.

Abstract: A programmable remote control is implemented using a standard personal computer. The computer controls the output of, for example, an infrared transmitter to control various devices such as televisions, stereos, videocassette recorders or cd players. The computer can alter the type of commands issued from the transmitter based upon a command structure stored on a hard disk within the computer. This database is updatable from a variety of sources.

Abstract: A method of scheduling a plurality of data flows in a shared resource in a computer system, each of the data flows containing a plurality of data cells including the steps of providing a scheduler in the shared resource, initializing the scheduler to receive the plurality of data flows, receiving a first data flow in the scheduler, said first data flow having a first flow rate, receiving a second data flow in the scheduler, said second data flow having a second flow rate, scheduling, by the scheduler, the first data flow and the second data flow such that the first flow rate and the second flow rate are less than an available bandwidth in the shared resource and a relative error is minimized between an actual scheduling time and an ideal scheduling time on a per cell basis, and repeating the steps of receiving and scheduling.

Abstract: The sense amplifier of the present invention senses the logic level of a digital data element that is conveyed using a low voltage swing signal. That sensing operation occurs relatively soon after the logic level of the data element begins to be established at the input of the sense amplifier. Such a sense amplifier is referred to as having increased sensitivity due to an improved common mode rejection ratio. The common mode rejection ratio is improved by turning-on a pair of evaluate transistors in a successive manner. The sense amplifier includes a pair of discharge paths for allowing a charge, stored on associated internal signals, to be discharged at a given rate that is proportional to voltage levels of the associated data signals. Those data signals are isolated from the discharge paths such that the associated logic levels are not affected by the above mentioned discharge operation.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.

Abstract: A database co-processor for efficient sequential data retrieval from a relational database is provided which is adapted for connection to a host system via a two-way bus network. The database co-processor includes an interface unit connected to receive and transmit data over the two-way bus network, and a database engine connected to the interface unit by input and output buses. The database engine includes a relevant field selection unit for storing selection criteria relevant to a database query raised by the host system processor. A comparator, which is incorporated into the database engine, compares input candidate data received on the input bus in accordance with the selection criteria and produces a result. The database engine further includes memory for the storage of output candidate data received on the input bus.

Abstract: Power consumption of an audio system of a computer is controlled, in response to an audio power management event, by altering the operation of the audio system in a manner that changes the power consumption of the audio system.

Abstract: The present invention relates to a low latency serial bus system for shadowing registers between first and second digital devices. Either the first device or the second device may initiate a data transfer cycle on the serial bus when data in a shadowed register of that device has changed. The data transfer cycle includes a first frame where data is transferred from the first device to the second device and a second frame where data is transferred from the second device to the first device. The devices do not initiate a subsequent data transfer cycle for changed data if the changed data can be transferred in the current data transfer cycle.

Abstract: The present invention is a process-pair resource manager for use in a transaction processing system. The process-pair resource manager includes a concurrent aspect and a serial aspect. The concurrent aspect provides an object-like interface to a protected resource. An application program participating in a transaction accesses the protected resource by passing messages to the concurrent aspect. The concurrent aspect adds a description of each message as well as the result of processing each message to a transaction record. At the conclusion of a transaction, the concurrent aspect passes the transaction record to the serial aspect. The serial aspect then replays the transaction, using the transaction record. If the replay of the transaction is consistent with the transaction as recorded in the transaction record, the serial aspect sends a message to the concurrent aspect voting to commit the transaction. In turn, the concurrent aspect sends a message to the transaction manager forwarding the commit message.