Abstract: A computer system and method for remotely allocating memory space in a memory of a remote computing device comprising a local IOP which remotely allocates memory space, for use by the local IOP, in a memory of a remote computing device. The local IOP detects a condition requiring a remote memory allocation and sends a remote allocate message to the remote computing device. The local IOP also performs an internal memory allocation in response to a remote allocate message initiated and sent by the remote computing device. The memory is partitioned to allocate distinct portions of memory for use by the IOP and the remote computing device. An allocation verification table contains data pertaining to the authorization of remote computing devices to allocate memory in the local IOP. The local IOP checks the allocation verification table to verify that the remote computing device is authorized to allocate memory.

Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein. Spring elements contained in the latch configuration can include biasing to overcome tolerance build-up and plastic creep from repeated and long term usage.

Abstract: A method and an apparatus reduces aliasing artifacts in images defined by pixels. A pixel is partitioned into subpixel locations from which sample points are selected. A fragment of the image is determined to be visible at at least one of the sample points. A fragment value associated with that fragment is stored. Each sample point at which the fragment is visible is linked to the stored fragment value. A color of the pixel is computed from the stored fragment values to reduce the aliasing artifacts in the image.

Abstract: An embodiment of the present invention discloses a technique for concealing a peripheral memory transaction on a local bus within a peripheral controller from a host system bus. In the preferred embodiment both the local bus and the host system bus are PCI buses. The technique is implemented when a peripheral memory transaction is detected on the local bus. In a disclosed embodiment, the peripheral memory transaction is detected by monitoring command and byte enables (CBEs) and five upper address bits (AD[31::27]) of the local bus. A peripheral memory transaction is indicated when a memory transaction on the local bus is directed to an upper 128 MB of 4 GB host memory. When a memory transaction is detected to the upper 128 MB of memory the transaction is intercepted. The interception is accomplished by blocking the CBEs on the local bus from a peripheral interface.The peripheral interface in the preferred embodiment is a standard PCI--PCI bridge which couples the local bus to the host system bus.

Abstract: A computer system that implements communication support with a minimum amount of main memory. The computer system provides a Basic Input/Output System (BIOS) for execution in Random Access Memory (RAM). Included in the BIOS is the communication initialization and runtime code. Upon initialization, the communication initialization code is executed, configuring and initializing communication devices, including a Universal Serial Bus (USB) device. After the initialization, the runtime communication code is moved to a secure memory, such as System Management Mode (SMM) memory. The runtime communication code is executed in response to an interrupt to the secure memory. If the secure memory is SMM memory, then a SMI will trigger the execution of the communication code. The main memory is not accessed to execute the runtime communication code.

Abstract: A circuit for isolating a device from a bus includes a switch and control logic. The switch has a control input and is coupled between the bus and the device. The bus includes a first plurality of bus lines, including a first grant line. The device includes a second plurality of bus lines, including a second grant line. The control logic is coupled to the control input of the switch and adapted to detect a bus isolation event, and generate a bus isolation signal in response to the bus isolation event. The control logic provides the bus isolation signal to the control input of the switch, and drives the voltage on the second grant line to a predetermined voltage in response to the bus isolation signal. The predetermined voltage is independent of the voltage on the first grant line. A method for isolating a device from a bus includes detecting a bus isolation event. An isolation signal is generated in response to the bus isolation event. The device is isolated from the bus in response to the isolation signal.

Abstract: An apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device, such as a bus bridge.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: A technique for reliable passage of handshaking information between a cellular modem and a land modem. Instead of bare transmission over a voice channel connection highly susceptible to signal fading and dropout, the initial modem handshaking exchange is instead FSK-encoded and broadcast using a network data signalling methodology already used to reliably pass signalling information between the base and registered mobiles. Automatic retransmission request signalling and transmission redundancy may be implemented to insure successful receipt at the receiving end of the radio link. Once received and verified, handshaking information is decoded and delivered to the destination modem in the appropriate format along cleaner fixed pathways. Reliable handshaking operations are contemplated whether the destination modem is a cellular modem registered in auto-answer mode (land-originated data call), or a land modem (mobile-originated data call).

Abstract: A shared bag, for collecting objects used in object oriented programming, implemented as a process pair resource manager intended to provide concurrent access to multiple threads. The process-pair implementation includes a concurrent aspect and a serial aspect. Each thread gains concurrent access to the shared bag through a registered transaction. The multiple threads can concurrently access the shared bag by passing messages to the concurrent aspect in order to add objects to, or remove objects from the shared bag. The concurrent aspect adds a description of each message, as well as the result of processing each message, to a transaction record associated with the transaction under which the thread is registered. The identity of each removed object is also recorded by the concurrent aspect in the transaction record. At the conclusion of a transaction, the concurrent aspect passes the transaction record to the serial aspect. The serial aspect then replays the transaction, using the transaction record.

Abstract: A multimedia system for delivering multimedia content to customer premises equipment via a circuit of a communications network includes a plurality of servers connected to a plurality of disk systems by a switch and a local area network. The switch includes an arbiter and a plurality of switching elements connected as a crosspoint mesh. Each switching element includes one or more gates and a register connected to a first input of each gate. The arbiter can set the registers to a logical one to allow selected multimedia content to flow through the gate either from the disk systems to the servers, or from the servers to the disk systems in response to customer demands. The local area network is used to transport switching messages from the servers and the disk systems to the arbiter.

Abstract: In a computer system having redundant SCSI controllers cards, a SCSI controller interface for receiving multiple interchangeable SCSI controller cards is configured so that the data bus paths between each of the SCSI controller slots and the controller circuitry do not cross.

Abstract: A method and system for enabling/disabling automatic encryption engines/algorithms using the Global Positioning System for country/locale verification and compliance with federal encryption export statutes.

Abstract: A series of modular plugs insertable into a row of connector sockets mounted on a circuit board to be tested are secured to a specially designed support structure which enables the plugs to be simultaneously mated with the sockets to thereby substantially reduce the required test connection time and to enable the plugs to be coupled with and uncoupled from the sockets without subjecting the plug cables to appreciable handling stress. In one embodiment thereof the support structure may be manually moved toward the sockets to effect the coupling of the plugs with their sockets, and a movable latch plate member is carried by the support structure for use in simultaneously unlatching the inserted plugs from their sockets. In another embodiment thereof the support structure is stationarily secured to a specially designed test stand assembly which is operable to move the circuit board toward the stationary plugs to effect the desired plug/socket test interconnection.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.

Abstract: A hardware security password mechanism that allows administrators to manage the passwords more easily by managing them centrally on a network rather than on an individual system. Further, each individual machine interacts with the network to allow the system administrator to lock down the hardware features without having any local, hardware-based password mechanisms.

Abstract: A computer system and new method of generating peripheral device configurations in a computer system having multiple types of system resources is disclosed. The method defines a resource priority list for the system resources and configures a device a resource type at a time based on the resource type priority list. The resource priority list is a function of the number of resource items for each system resource and the available resources in the computer system. The method thus serves to minimize the number of testing or checking iterations in configuring a device, whereby significant improving device configuring and conflict resolution in a computer system.

Abstract: Method and apparatus of controlling a power state of a computer, the computer being connected to a monitor having a power control button. The computer is connected to the monitor over a video cable, and activation of the power control button is communicated to the computer over a wire in the video cable. In response to the activation signal, a system management interrupt is generated to invoke an SMI handler to change the power state of the computer. The power states of the computer include an ON state, an intermediate power state (such as Sleep state), and a suspend state (such as Soft-Off state).

Abstract: A new virtual memory system is disclosed having a virtual address space including a gap of inaccessible virtual addresses within the virtual address space. A new virtual memory allocation routine is disclosed providing a starting address of accessible virtual addresses allocated to a currently executing process in a response to a request. The accessible virtual addresses are virtually contiguous, and include no addresses from within the gap of inaccessible virtual addresses. A new virtual memory deallocation routine is further disclosed providing deallocation of ranges of virtual addresses which may or may not include addresses within the inaccessible gap.

Abstract: A tower computer housing has a molded plastic exterior wall portion with an access opening therein, a molded plastic access door, and a specially designed hinge structure that supports the access door on the housing for pivotal movement relative thereto between closed and open positions in which the door respectively covers and uncovers the access opening. The hinge structure includes spaced pairs of hinge pins and cam arms molded integrally on opposite ends of the access door, and spaced apart first and second resilient mounting and spring tab sets molded integrally with the housing exterior wall portion. Each of these sets includes a resilient mounting tab having a mounting hole therein and positioned between an opposed pair of resilient spring tabs. The door pins are removably snap-fitted into the mounting tab holes, and each of the door cam arms is positioned between and slidingly engages a pair of the spring tabs.