Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A programmable operational system for managing devices participating in a network including a collection of notices, operation logic that filters the collection of notices based on at least one criteria and that generates at least one operation indicative of a state change of the network, and an automation engine that uses the at least one operation to perform at least one process in response one or more operations. The collection of notices, generated by a plurality of routines, are indicative of the state of hardware, software, and user actions that comprise the network including the state or status of one or more of the devices participating in the network. The operation logic may include an operation engine and one or more operational groups. Each operational group may further include one or more operations, each including a filter and configuration information. The operation logic may further generate at least one job and store the job into memory, where each job references an operation.

Abstract: A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Abstract: An electronic commerce system includes a broker computer system having a database of scrip representing a form of currency, a vendor computer system having a database containing products which may be exchanged for the scrip, a consumer computer system with which a user may initiate transactions with the scrip, and an agent computer system to which the consumer can delegate rights to perform actions with the scrip. To delegate actions on scrip, the delegator provides the delegatee with a delegation having a list of the delegated actions. In addition, the delegator determines a delegation scrip secret (DSS) and a delegation pass phrase (DPP) and securely passes these to the delegatee. The delegatee uses the DSS to authenticate itself to servers accepting the scrip and uses the DPP to encrypt the DSS while the scrip is stored by the delegatee. To perform an action with delegated scrip, the delegatee sends a request for the action to a server.

Abstract: A device for seamlessly providing 10BASE-T compatible data communications over an ordinary single twisted pair home phone line between multiple computers, between computers and peripherals, and between multiple peripherals. Each component that is to communicate over the home phone line will have a 10BASE-T compatible network interface card (NIC) for interfacing with the device. A transmit/receive switch is used to switch the device between a transmit mode and a receive mode. When signal are being transmitted from a component a Manchester coder decodes signals received from the NIC. A differential converter is used to convert the differential signal received from the NIC to a single signal. A modulator is used to modulate the signal to a RF signal using a modulation scheme such as PSK, QPSK, QAM or MCM schemes. A filter is used to limit the bandwidth of the modulated signal and a driver is used to amplify the signal to match the impedance of the phone line.

Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.

Abstract: A technique for identifying multiple circuit components. More specifically, a technique for identifying the location of electrical components, such as memory cartridges which have been disposed on a substrate, is described.

Abstract: A system for execution of code during power-on-self test (POST), the system including a mass storage device for storing computer programs; a microprocessor connected to the mass storage device, the microprocessor including an execution unit; a general purpose register connected to the execution unit, the general purpose register for storing a first data element; an MMX unit including a plurality of MMX registers, the MMX unit connected to the general purpose register, wherein the plurality of MMX registers are configurable as a virtual stack; a storage device connected to the microprocessor, the storage device for storing BIOS instructions; and a plurality of BIOS instructions stored on the storage device, the plurality of BIOS instructions readable by the microprocessor to thereby cause the microprocessor to execute a virtual stack push instruction wherein the first data element is moved from the general purpose register to a first of the plurality of MMX registers; and execute a virtual stack pop instructio

Abstract: Improved techniques for rapid and efficient delivery of objects from a network (e.g., the Internet) to users. The improved techniques can be utilized in a variety of apparatuses, including a proxy system or an acceleration apparatus. Such a proxy system operates to produce an accelerated version of content information from the network, cache the accelerated version (and possibly original versions) for subsequent requests for the same information content, and supply the accelerated version of the information content to a requesting user.

Abstract: A facsimile machine provides firmware to remotely activate and deactivate fax forwarding. The firmware enables a user to remotely activate or deactivate fax forwarding through an email, fax, or a telephone. The facsimile machine may be set by the user to activate and deactivate fax forwarding at a predetermined activation time and a predetermined deactivation time. If fax forwarding with local printing is activated, the facsimile machine locally prints a fax after the fax is forwarded. The facsimile machine may be a multifunctional peripheral.

Abstract: A computer system, bus interface unit, and method are provided for securing certain devices connected to an I2C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I2C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I2C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I2C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I2C bus or addressed device thereon.

Abstract: Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Abstract: A method for executing trusted commands, in which a trusted command is first received from a user at a user terminal and parsed by untrusted code; then passed to a trusted computing base for execution. The trusted computing base displays to the user for confirmation indication of what is to be done. Confirmation of the commands prevents unauthorized modification of the commands and increases system confidence. A randomly (or pseudo-randomly) generated process identifier is employed to verify the existence of a trusted path.

Abstract: Disclosed is a five-step process for producing closed captions for a television program, subtitles for a movie or other uses for time-aligned transcripts. An operator transcribes the audio track while listening to the recorded material. The system helps him/her to work efficiently and produce precisely aligned captions. The first step consists of identifying the portions of the input audio that contain spoken text. Only the spoken parts are further processed by the invention system. The other parts may be used to generate non-spoken captions. The second step controls the rate of speech depending on how fast the operator types. While the operator types, the third module records the time the words were typed in. This provides a rough time alignment for the transcribed text. Then the fourth module realigns precisely the transcribed text on the audio track. A final module segments the transcribed text into captions, based on acoustic clues and natural language constraints.

Abstract: A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Abstract: A network provides color translation between a server side application and a web browser application. A color object created on the server side is reduced into the individual color components defining the color property for the object. These discrete color components are then converted into numerical values representing the intensity of the respective component. The color components are then combined into a format usable by a web-based computer application. For objects including text information, the color property for the text is automatically determined, based on the translated color object, to achieve a high contrast between the background color and the foreground or text color.

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.

Abstract: Improved techniques for remotely accessing account information through the Internet are disclosed. The remote access techniques provide security measures so that unauthorized access is unlikely even though the Internet is utilized. Assuming access is authorized, the requested account information can be acquired and then presented to a requester via the Internet in a format suitable for the type of the requested account information. In addition, as an additional security measure, the invention may also filter out any account holder identifying information from the requested account information such that the account information presented to the requester does not identify the account holder.