Abstract: A computer system for flashing Extended System Configuration Data (ESCD) and associated variables to a flash read-only memory (ROM) is provided. During Power-On-Self-Test (POST) code, a ROM image is copied from an ESCD sector of a read-only memory to an ESCD original buffer and an ESCD write buffer. The ESCD write buffer may be updated by POST code. Following the POST operations, the contents of the ESCD write buffer are copied to an ESCD runtime buffer. The contents of the ESCD original buffer or the ESCD sector are compared to the contents of the ESCD runtime buffer. If the contents of the ESCD runtime buffer differ from the contents of the compared buffer or sector, SMI code flashes the ROM image in the ESCD runtime buffer to the flash ROM. If the ESCD runtime buffer is the same as the contents of the compared buffer or sector, a ROM flash it not performed. POST is then exited and the computer system is booted.

Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps.

Abstract: A system is disclosed for allowing surprise insertion and removal of a peripheral device from the bays of a portable computer system. The peripheral device may be inserted or removed when the portable computer system is powered off, powered on, or in standby or sleep mode. The peripheral device may be any one of a multitude of devices corresponding to the IDE, ATAPI or FLOPPY standard. Insertion or removal of the device is operating system and BIOS independent. A constantly executing detection process determines when a peripheral device has been inserted into or removed from a bay. A multilevel device driver allows layered functionality and simplified interfacing between the operating system and computer system and peripheral hardware. Layering of the multilevel device driver allows simplified BIOS firmware. Identification and configuration of the peripheral device is handled by a IDE/ATAPI bridge device driver that is capable of recognizing any IDE, ATAPI or FLOPPY device inserted into a bay.

Abstract: A method and apparatus for displaying multiple communication network monitors having multiple monitoring intervals on a single graphical display. A user, through an input device, selects an object relating to a network monitor to be displayed on a graph and a processor retrieves network data from a communication network pertaining to the selected object. The display values for a line on the graphical display represented by the monitor are calculated by the processor such that, the line and any previously existing lines, are coherent in that the displayed parameters are consistent across the lines. Once the display values are calculated, the line is displayed on an output device. The user may additionally modify parameters associated with the monitor or add or delete a monitor. If the user modifies a parameter, the processor modifies the parameter and updates the display.

Abstract: A method and system of quorum negotiation utilizing power mains. Unlike current systems, this communication is provided as a secondary channel, with the primary channel being a standard network system. By using this technique, if the heartbeat is lost over the primary communication system, the secondary, power-mains system can be used to check the heartbeat to validate whether or not the “lost” system is still in operation. If communication cannot be established over the power mains, it is assumed that the “lost” system is down and should be dropped from any cluster.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A portage computer case whether in a closed state or open state permits a user to exercise control and monitor certain operating features. The user may toggle a control switch to place the computer system in a secondary operational mode, determine when a computer system is in a secondary operational mode, and adjust a digital master volume control during the secondary operational mode. The portable computer system includes a status indicator for indicating when a computer is in a secondary operational mode, digital master volume control buttons operable in a secondary operational mode, and a control switch for placing the computer system in a secondary operational mode. The status indicator, volume control buttons, and control switch are preferably provided on a top surface of the bottom shell of the portable computer for convenient access by a user.

Abstract: A system for providing a signal indicating whether a process is installed and providing improved voltage regulation. A contact is selected and isolated from an array of ground contacts and is further coupled with circuit for generating an INSTALL signal. A capacitor and pull up resistor coupled to a supply voltage, ground and the isolated contact form a signal line at a common node such that a circuit to ground is completed through the processor and the isolated contact when the processor is plugged in and a direct signal indication of the presence or absence of the processor is provided. Voltage sense lines of a Voltage Regulation Module (VRM) are coupled directly to processor contacts isolated from an existing voltage supply contacts coupled to the supply plane of a supply voltage within the circuit board providing improved regulation without adversely affecting power supply current capacity considerations.

Abstract: A battery casing is adapted to fit into at least two different receiving bays of different sizes. The casing includes an adapter panel which is movable into at least two positions. Moving the adapter panel to the first position increases the effective width of the casing, and allows the battery to be inserted securely into a first receiving bay. Moving the adapter panel to the second position maintains the original width of the casing. This allows the battery casing to be inserted securely into a receiving bay, which has the same width as that of the original casing.

Abstract: A circuit for generating a double-edged POWERGOOD signal to a P6 processor after power-up. After a power supply circuit asserts a signal which indicates that computer system power supply voltages are stable and within threshold levels, the circuit drives the POWERGOOD signal high. A first period later, the circuit drives the POWERGOOD signal back low. The POWERGOOD signal is maintained low for a second predetermined period. Finally, the circuit drives the POWERGOOD signal back high again, and the POWERGOOD signal is maintained high for as long as the power supply circuit indicates that computer system power supply voltages are stable.

Abstract: The present invention is a power distribution assembly for distributing power about a rack mounted server system. In particular, each chassis of a rack mounted server system is provided power through a power distribution assembly that is hinged to a back of the rack of the server system. Each of the power distribution assemblies may be in either an open position or a closed position. In a closed position, each of the power distribution assemblies is rotated to lie very close to a backplane board of a chassis of the server system. In an open position, each of the power distribution assemblies is swung around so that full access may be had to the backplane boards of the chassis in the server system.

Abstract: A power management scheme for a computer system prioritizes battery charging. The scheme includes determining when the output of a power adapter, which powers a computer and a battery subsystem, has reached or is about to reach a threshold which may be the power budget for the computer system. When this happens, rather than throttling battery charging, the system throttles back an aspect of the computer. Alternatively, after the computer has been throttled back, if the power budget still is being exceeded or is about to be exceeded again, then battery charging can be throttled back. In yet another embodiment, battery charging can be throttled first, followed, if necessary, by computer throttling.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: The present invention provides for a method and an apparatus for encoding coherency tag information for a plurality of busses. A first processor bus is coupled to a host controller. A second processor bus is coupled to a host controller. The host controller is coupled to a single coherency tag bank. Coherency tag data from the first processor bus and the second processor bus is stored into the coherency tag bank. A location of a data set sought by the first processor and the second processor is determined using the coherency tag data.

Abstract: A multipoint digital simultaneous voice and data (DSVD) conferencing system includes a plurality of local DSVD modems to communicate with a plurality of remote DSVD modems and a bridge to transfer data and digitized voice signals among the plurality of remote DSVD modems by way of the plurality of local DSVD modems. A plurality of simultaneous conferencing connections are maintained between the plurality of local DSVD modems and the plurality of remote DSVD modems. The system support a multipoint DSVD conferencing session connecting the plurality of remote DSVD modems.

Abstract: Apparatus is provided for a heat transfer assembly for direct attachment to a high heat generating chip, which assembly includes a pump, air side heat exchanger mounted adjacent to a fan and a heat transfer plate which is attached to the high heat generating component for dissipating heat from such component under operating conditions. In another embodiment, apparatus is provided for dissipating heat from a hard disk drive including a U-shaped heat exchange clip resiliently mounted on opposite surfaces of a hard disk drive. In another embodiment, apparatus for dissipating heat from a hard disk drive includes a generally rectangular plate for mounting on the top or bottom of the hard disk drive. And, in another embodiment, apparatus is provided transferring heat from a vertical array of hard disk drives, which apparatus includes one or more panels interposed between adjacent vertically disposed hard disk drives.

Abstract: A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.

Abstract: A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices.

Abstract: A clock control technique allows reducing the power consumption of devices connected to a computer bus. Individual idle devices can be disconnected from the bus clock by a device clock controller and placed in a low-power state without waiting for all devices on the bus to go idle. When individual devices are idle, transactions on the bus are monitored and unclaimed transactions are claimed by the device clock controller, which then forces a retry of the transaction and reconnects the clock to the idle devices. This brings these devices from the low-power state to a full power state, where they are capable of claiming the transaction when it is retried.

Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requester and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.