Abstract: A personal computer provides security features enabling control over access to data retained in the computer. The computer is secured by having the system ROM provide a password at power-on to a security device which controls access to the secured features. Once a password has been downloaded to the security device, a Protect Resources command is issued to the security device. To gain access to the secured feature after boot-up, the user provides the correct password to the security device and waits for approval from the security device. Since the security device only verifies the password and does not divulge it, security of the system is enhanced. Once access to protected resources is no longer required, the computer issues another Protect Resources command to the security device to once more lock access to the protected resources.

Abstract: A multi-functional computing device that is configurable for a plurality of applications. The technique includes a space saving and configuration technique utilizing multiple joints disposed between multiple sections to facilitate rotational orientation of the sections to adapt to space limitations and other characteristics of a desired environment or application. The multiple sections include a display assembly and a housing assembly for computing components.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A method for broadcasting packets in a network that includes a plurality of switches. The network can logically be represented by a spanning tree plus cross-links. In order to avoid deadlock during a broadcast, a broadcast packet is sent from an originating switch to a root switch of the network, and a copy of the packet is sent from a current switch to all descendant switches when all copies of the packet have been received in the current switch.

Abstract: A manageable desktop computer system and an associated method for managing a plurality of manageable devices. The computer system includes a storage facility, a registry and a plurality of manageable devices coupled to a hardware component interface (HCI). The HCI includes a dynamic linked library (DLL) which contains a first data structure which describes available management information for each one of the plurality of manageable devices and a function calls area which contains locational information as to where, within the storage facility, the registry or the plurality of manageable devices, the available management information is maintained.

Abstract: A self-orienting logo assembly so that the logo is always in a horizontal orientation. In the preferred embodiments the logo is located on a disk. The disk is weighted or otherwise designed to have its weight distributed nonuniformly. The disk is located inside a housing. The housing is attached to the computer or other equipment bearing the logo. When the housing is located in a vertical plane the disk rotates to allow the logo to remain horizontal. The disk can be rotationally mounted to the housing or can be suspended in liquid. In an alternate embodiment the disk can have a magnet incorporated so that when the disk is in a horizontal orientation it can act as a compass. In another embodiment a portion of the disk is removed and the housing contains an additional logo or wording. The rotation of the disk can then cover or expose the additional logo or wording.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Abstract: Disclosed is a coaxial cable bundle interconnecting a base and display in a notebook computer. The cable bundle includes outer cable layers surrounding a bundle of multiple cables. Each of the multiple cables includes a center conductor that is a 40 AWG wire surrounded by a dielectric medium. On top of the dielectric medium is a twisted served shield helically wrapped around the dielectric medium and the center core conductor.

Abstract: A system for integrating task and data parallelism in a dynamic application that includes at least one task for processing an input data stream to produce an output data stream replaces the at least one task with the following components. A splitter task for partitioning the input data stream into a plurality of data chunks. A plurality of worker tasks for processing subsets of the data chunks, each worker task being an instance of the at least one task, and a joiner task combining the processed data chunks to produce the output data stream.

Abstract: Solutions for reducing latencies in enterprise operations and business processes adaptation particularly as related to enriched publish and subscribe are proposed by the present invention. These solutions are implemented in a zero latency enterprise (ZLE) framework that allows the enterprise to integrate its services, applications and data in real time. Namely, an enterprise equipped to run as a ZLE is capable of integrating, in real time, its enterprise-wide data, applications, business transactions, operations and values. An operational data store operates as an information broker between the applications such that applications publish messages to the central repository and subscribe to messages from the central, rather than exchange request-response messages directly with each other. Thus, enriched publish and subscribe improves information synchronization between applications and reduce the number of request-response messages the applications would otherwise exchange.

Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.

Abstract: A computer system having integrated remote console functionality. Cycles intended for a video graphics controller are snooped to acquire the video data or control information contained in the cycle. Analysis is performed on the video data to detect sequential or repetitive operations. The video data is encoded into higher level primitives, if possible. The video data and primitives are held in a first-in-first-out (FIFO) memory until the FIFO reaches a critical level, or a staleness timer times out. Special firmware executed in system management mode reads the FIFO and converts the video data and primitives into conventional ASCII text or the required format. The firmware also maintains a copy of the video frame buffer to further encode the video data, if possible. The firmware then transmits the conventional ASCII text via a modem to a user stationed at a remote computer system.

Abstract: A system for facilitating airflow in a processor-based device, such as a server. The system is particularly amendable for use in low profile devices that inherently have reduced space for airflow. The system utilizes a tray deployed along a base wall or other wall of the device chassis. The tray is utilized to secure a cable or cables that would otherwise inhibit airflow.

Abstract: A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell.

Abstract: Methods and arrangements are provided for allowing various devices to communicate data over standard twisted pair wire within a confined region, such as a home environment. The methods and arrangements employ radio frequency (RF) communication techniques to modulate and transmit data signals over existing twisted pair phone lines at RF frequencies. The RF transmitted data can be detected over limited distances by other similarly configured devices. The RF transmitted data is then received and demodulated to regenerate the original data. The methods and arrangements also allow the data transmission to be conducted in accordance with conventional CSMA/CD techniques/protocols. Thus, for example, Ethernet network configured devices can be seamlessly interconnected using the methods and arrangements of the present invention without requiring that additional and/or upgraded wiring be installed in the home environment.

Abstract: A system to mount several electronic devices within a one EIA unit high rackspace is presented. The system includes a mounting chassis that is securely fastened to a standard 19″ EIA electronics rack. The chassis includes dividers that define at least two full length ports in which the electronic devices are slidably engaged. Furthermore, each port defined by the mounting tray includes hot-pluggable, blind-mate sockets to receive corresponding hot-pluggable, blind-mate connectors upon each electronics package. These packages are engaged and disengaged to and from the ports within the rack at will, thus allowing for more servers to be efficiently and accessibly stored within the confines of a 1-U rackspace with interchangeability than was previously possible.

Abstract: Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Abstract: An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

Abstract: In one aspect, the invention is a battery fuel gauge for a cache card comprising a charging circuit for charging at least one battery and a decrementor circuit for counting the amount of time system power is removed from the battery.

Abstract: A computer system having thermal control logic that efficiently cools the computer system. In accordance with one embodiment of the invention, the thermal control logic couples to a CPU module and a fan. The CPU module includes a pair of temperature response elements. One temperature response element located near or on the CPU core logic or die on which the CPU is fabricated. The other temperature response element is located near or on an exterior surface of the CPU module. The thermal control logic monitors the temperature of recorded by each temperature response element and controls the speed of the fan and the frequency of the CPU core clock independently. Preferably, the thermal control logic adjusts the fan speed as a function of the temperature recorded by the temperature element adjacent an exterior surface of the CPU module. The thermal control logic also adjusts the frequency of the CPU clock signal as a function of the temperature recorded by the temperature response element adjacent the CPU core.