Abstract: A method of preventing current hogging in parallel connected transformers, and an apparatus for efficiently implementing the method are presented. Current hogging occurs when synchronous power converter transformers operate in a low output current mode. Low output current demands are typically meet by adjusting the duty cycle of the transformer to a low level. This results in the catch FET maintaining a low resistance path to ground for long time periods and allows a stronger one of the parallel power converter transformers to sink current to ground through a weaker transformer. The method consists of using a current sensor to detect low or negative output currents, and then driving the transistor providing the path to ground to an off state.

Abstract: A hot-pluggable disk drive is supported on a carrier structure which is slidably and removably insertable rearwardly into a sheet metal cage portion of a computer system in a manner releasably coupling an SCA connector on a rear end of the drive to a corresponding electrical connector on a backplane structure within a rear interior portion of the cage. Heat generated by the operation of the disk drive is removed by forced convection via a flow of air forced through the cage by a suitable cooling fan. This convective cooling is conductively augmented by a pair of finned metal heat sink portions of the carrier which are movably carried by a base wall portion thereof, clamped against opposite sides of the supported disk drive, and positioned in the cooling air flow through the cage. Resilient thermal interface pad members are compressed between the finned heat sinks to improve the efficiency of heat conduction from the disk drive sides to the heat sinks.

Abstract: The invention provides a method for acquiring a lock in a network of processors with globally ordered remote-writes. A process requesting a lock changes an associated ticket number from zero to one. Next, the process determines if every other process attempting to acquire the lock has a ticket number of zero. If true, the request for the lock is immediately granted. Otherwise, if false, the process changes its ticket number to a value greater than that of every other process, and the process waits until its ticket number is the lowest non-zero ticket number, in which case the lock is granted with mutual exclusion.

Abstract: A memory interface controller employs a DATUM multiplier within a destination address to perform DATUM RAID operations. If destination data is in an XOR memory address space, then the multiplier can indicate to multiply source data by the multiplier and XOR that resulting data with the destination data. The DATUM multiplier can be read in response to detection of a memory command. The multiplier alternatively can be used in connection with an input/output bus write command to write source data from the input/output address space to an XOR memory address space. In response to such a write command, the input/output bus data in the input/output address space is multiplied by the multiplier; that resulting data is XORed with the destination data in the XOR memory address space. The multiplier in this case can be within an input/output bus address associated within the input/output bus data.

Abstract: A method and apparatus for presenting the multiple processors of a cluster as a single virtual host to a network wherein the processors are communicatively coupled among themselves and to a network interface. The network interface is communicatively coupled to the network. One of the processors is designated a primary parallel I/O processor. One address is advertised on said network for said multiple processors, and filter trees in the network interface direct the interface to forward packets from the network addressed to that address to the primary parallel I/O processor. Later, the filter tree is modified to direct the network interface to forward a specific subset of the packets directly to a particular processor.

Abstract: A computer system according to the present invention implements a self-modifying “fail-safe” password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.

Abstract: A computer system comprises a variety of components transmitting variable-rate heartbeats to a heartbeat monitor, each heartbeat indicating that the component is functioning properly. In addition, selected components serve as proxies by transmitting heartbeats to indicate that another component is functioning properly. In the preferred embodiment, one or more central processing units (CPUs) transmit heartbeats to indicate proper CPU functioning, while a bridge logic device and a network interface card (NIC) transmit heartbeats as proxies for a memory device and an external computer system, respectively. The heartbeat monitor is capable of determining initial heart rates for each component and is further capable of adaptively varying the heart rates thereafter. If the age of the heartbeat sender is relatively young, then a relatively slow heart rate is specified. Faster heart rates are specified for older components.

Abstract: A technique for providing hardware interrupt simulation using the interprocessor interrupt mechanism of the local Advanced Programmable Interrupt Controller (APIC) on a Symmetric Multiprocessor (SMP) System running Windows NT is disclosed. The interrupt simulation is performed by first determining the Interrupt Request (IRQ) vector that is associated with a particular system device driver. In the case of devices being emulated, the determination of the IRQ vector is done by intercepting the messages from the interrupt invoking procedure. The IRQ vector provides a pointer to the device driver's Interrupt Service Routine (ISR). After the device driver's ISR is connected to the appropriate interrupt vector entry in the Interrupt Descriptor Table (IDT), the vector number is combined with the local APIC constant and followed by a 32-bit write operation into the lower part of the Interrupt Control Register (ICRL) of the local APIC.

Abstract: A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

Abstract: An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The semiconductor device has a pad for receiving a signal. The technique uses an ESD protection circuit that includes a voltage limiter having an input to receive a control voltage that is independent of a pad voltage on the pad; an output to provide, in response to the control voltage, a limited voltage having a magnitude that is less than a magnitude of the control voltage when the control voltage is non-zero and in a steady state; an arrangement of stacked transistors interconnected between the input and the output of the voltage limiter; and a pull-up transistor that is interconnected between the pad and the output of the voltage limiter. A magnitude of the pad voltage is less than the control voltage when the semiconductor device is in a normal operating mode.

Abstract: A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.

Abstract: A multi-user bus is divided into a number of bus portions, one for each user. Each bus portion is coupled, at one end, to one of the multiple users and through an impedance matching network to the other bus portions in a star configuration. The disclosed embodiment teaches various resistive impedance matching networks.

Abstract: A computer microprocessor has a housing portion with a recess formed in a top side wall thereof, and a die portion inset within the recess. Operating heat from the die is removed by heat dissipation apparatus which automatically adapts to variations in the microprocessor bond line thickness and includes a sheet metal EMI shield wall overlying the microprocessor and having a condensing end portion of a thermosyphoning heat pipe secured to its bottom side, with an evaporating end portion of the heat pipe overlying the die recess and being resiliently deflectable toward a phase change thermal pad mounted on the top side of the die and inset into the housing die recess. A metal heat sink member is rotatably mounted on the heat pipe evaporating end portion and has a flat bottom side and an arcuate top side.

Abstract: A technique for reliable passage of handshaking information between a cellular modem and a land modem. Instead of bare transmission over a voice channel connection highly susceptible to signal fading and dropout, the initial modem handshaking exchange is instead FSK-encoded and broadcast using a network data signalling methodology already used to reliably pass signalling information between the base and registered mobiles. Automatic retransmission request signalling and transmission redundancy may be implemented to insure successful receipt at the receiving end of the radio link. Once received and verified, handshaking information is decoded and delivered to the destination modem in the appropriate format along cleaner fixed pathways. Reliable handshaking operations are contemplated whether the destination modem is a cellular modem registered in auto-answer mode (land-originated data call), or a land modem (mobile-originated data call).

Abstract: A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art.