Abstract: An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data.

Abstract: A general purpose computer apparatus including a central processing unit, a main memory and a system bus. The general purpose computer apparatus further includes means for interfacing the central processing unit to the system bus and means for interfacing the central processing unit to an I/O bus. A housing encloses the central processing unit, the main memory and the means for interfacing, with the housing having a mechanical form factor corresponding to a disk drive housing.

Abstract: A notebook computer base housing has operatively disposed therein a CD ROM drive, a hard disk drive and a floppy disk drive, an AC/DC electrical power converter, a modem, a PCMCIA card bay structure and a battery. This internal provision of three drive units in addition to the other equipment within the base housing is facilitated from a space standpoint by the vertical stacking of the hard disk drive atop the CD ROM drive within the base housing. To dissipate the operating heat from these components within the base housing, a heat spreader plate is interposed between the CD ROM drive and the overlying hard disk drive, and the high heat-generating components—namely, the modem, the AC/DC converter, the PCMCIA card bay structure, and the computer processor—are closely grouped together, with the AC/DC converter in thermal communication with a second heat spreader plate.

Abstract: A method for generating system passwords derived from an external encryption algorithm and plain text user passwords entered during a secure power-on procedure. At some point during the secure power-up procedure, the computer system checks for the presence of an external token or smart card that is coupled to the computer through specialized hardware. The token or smart card is used to store an encryption algorithm furnished with an encryption key that is unique or of limited production. Following detection of the external token, the computer user is required to enter a user password. The user password is encrypted using the encryption algorithm contained in the external token, thereby creating a system password. The system password is then compared to a value stored in secure memory. If the two values match, the power-on sequence is completed and the user is allowed access to the computer system or individually secured resources.

Abstract: A database management system includes an execution engine that, upon rollback of an aborted transaction, has the ability to set fields of the rows that are updated or deleted by the transaction prior to aborting. In particular, when a select, update or delete statement includes a “set on rollback” clause, the respective table access operator of the execution engine modifies the “before image” of each row that is stored by the transaction log manager. The modified before image includes the field updates specified by the set on rollback clause. If a transaction associated with the statement aborts, when the transaction log manager restores the before images of each row that was deleted or updated by the transaction, the restored before images include the field updates specified by the set on rollback clause.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A computer system provides a unified password prompt for accepting a user power-on password or an administrator password. A password string entered by the system administrator at the unified password prompt is compared with a stored power-on password. If the user password string matches the stored power-on password, then access to system resources is granted. If the user password string does not match the stored power-on password, then the user password string is compared to a stored administrator password. If the user password string matches the stored administrative password, then access to system resources is granted. If the user password string does not match the stored administrative password, then the system administrator is given a predetermined number of times to enter a password string matching either the stored power-on password or the stored administrator password.

Abstract: A computer system having PCI devices, associates bus numbers with these PCI devices during computer system configuration. During startup of the computer system, startup software relies on the bus numbers associated with the PCI devices to find and configure the PCI devices for normal computer system operation. When a PCI/PCI bridge is added to an existing PCI bus, a new PCI bus is created. This may cause the bus numbers of some of the PCI devices to change. Unless the computer system configuration is run again, normal operation of the computer system may not take place because the startup or “boot” program may not be able to find and configure the affected PCI devices without knowing the correct bus numbers. Adding the PCI physical connector slot number to the information derived during the system configuration and storing same in non-volatile RAM enables the computer system to update any PCI device bus numbers that may have changed without having to rerun the system configuration software.

Abstract: A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiprocessor system. A processor of the multiprocessor system is configurable to evict from its cache a block of data. The selected block may have a clean coherence state or a dirty coherence state. The processor communicates a notify signal indicating eviction of the selected block to the memory controller. In addition to sending a write victim notify signal if the selected block has a dirty coherence state, the processor sends a clean victim notify signal if the selected block has a clean coherence state.

Abstract: A parallel, fault-tolerant computer system in which data is transferred between processes in a single CPU by two methods. In a first method, the data is copied each time it is transferred. In a second method, the data is not copied, but is passed through a shared memory, queueing system. The first method is used to ensure fault-tolerance and linear expandability. The second method is used to minimize the time required for inter-process communication. Use of the shared memory queueing system allows for faster communication between processes executing in a same CPU.

Abstract: A computer system incorporating capabilities for displaying the audio disk track number when the computer system is playing an audio disk. The computer system determines if a disk is present in the disk drive. If a disk is present, the computer system determines if an audio disk is present in the disk drive. If so, the computer system then monitors the disk drive. When the audio disk is played by the disk drive, the computer system displays the audio disk track number. The computer system then periodically polls the disk drive to update the audio disk track number. The computer system displays a battery gauge status when the audio disk track number is not being displayed. The status display is visible when the portable computer is in either an open or closed state.

Abstract: A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.

Abstract: A modular hinge includes a clutch module coupled to an extension arm for supporting an enclosure, such as a display enclosure for a portable computer. The clutch module and extension arm are fabricated as separate parts, and then assembled together to form essentially one permanent hinge. This arrangement allows the extension arm of the hinge to by-pass the prehardening heat treatment, which is required for the clutch module.

Abstract: An apparatus and method is disclosed for providing 10BASE-T Ethernet compatible data communications between multiple network elements, such as computers, computer peripherals, computerized appliances, and the like, over a two wire residential phone line. Each network element may include a 10BASE-T compatible network interface card (NIC) for interfacing between the network element and the residential phone line through the device of the present invention. A transmit/receive switch, set to a default receive position, is coupled between the two wire residential phone line and a NIC, each NIC having a transmit and receive wire pair. The NIC senses receive energy originating from the residential phone lines. When receive energy is no longer sensed at the NIC, a transmit signal may be generated by the NIC, placed on the transmit wire pair.

Abstract: A portable computer has pivotally connected base and display screen lid housings and is provided with a generally wedge-shaped auxiliary component housing which is releasably latchable to the bottom of the base housing and extends across only a rear underside portion of the base housing. The attached auxiliary housing representatively carries a CD/DVD media drive unit and a floppy disk drive unit, operatively couples them to various computer components in the base housing, and is configured to rearwardly and upwardly tilt he base housing keyboard at a predetermined comfortable typing angle when the base housing is placed atop a horizontal work surface such as a desktop.

Abstract: A method and system for controlling the power supply fan in a computer system. The speed of a power supply fan can be made directly proportional to the temperature of the power supply. The fan speed can also be controlled by a processor with software commands according to the temperature of the processor. The speed of the fan will be dictated by the higher of the two commands driving it. Therefore, the power supply fan can never be commanded by the processor to run at a lower speed than that required by its own thermal environment. A Fan Speed Control Circuit enables the computer system to command the power supply fan to run at a higher speed. The processor temperature can be monitored with a temperature transducer and analog signal conditioning circuitry.

Abstract: A high resolution image and at least two low resolution images are combined to produce a single image, partially high resolution, partially low resolution on a display. The high resolution image at least partially overlaps at least one of the low resolution images. This method of displaying images is referred to as foveal video. In another aspect of the invention, in a robotic telepresence system, a user station displays information received from a robot using foveal video.

Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value.

Abstract: A system and method for scheduling packets between multiple links of an adaptive set utilizes a destination register or a cache line associated with each of the alternate links of the network switch. Each of the cache lines holds the destination of the last packet that used the link. Upon arrival, a packet associatively checks the content of all cache lines. If it hits, then it uses the corresponding link; otherwise, the packet is scheduled according to a round-robin policy or other default policy.

Abstract: A system and method for maintaining a communications within a computer system after a data transport failure across a first link. Fail-over capability is attained by re-establishing communications across a secondary link using different transport mechanisms. Between two Input/Output Processors (IOPs) within a computer system, such as a server, a series of data transactions therebetween are queued until transaction completion. Upon detection of a failure condition between the IOPs across the first link, the IOPs engage fail-over mechanisms to preserve uncompleted data transactions until communications are re-established across the secondary link.