Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port (“AGP”) bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect (“PCI”) device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract: A SCSI device resides and communicates on the SCSI bus without that device being assigned a SCSI address or corresponding SCSI ID. The driver software on the host computer directs the SCSI initiator device to select itself as its target, so the initiator then only asserts one bit of the eight bit SCSI data bus. The SCSI device determines when a SELECTION phase is under way and then determines if only one bit has been asserted on the SCSI data bus. The SCSI device then responds to the initiator as being the target device, thus completing the SELECTION phase. The initiator and the SCSI device can then communicate as a normal initiator and target would during information transfer stages of the SCSI standard. This is all done without the SCSI device occupying a normal SCSI address.

Abstract: Volumetric data are rendered onto an image plane by first organizing the volumetric data into a plurality of blocks of data, each block of data including a plurality of voxels arranged in cubic structure. The blocks of volumetric data are stored in, and processed by a processor element array of a massively data-parallel computer system. For any viewing angle, a plurality of parallel rays are cast through the image plane to traverse the volumetric data. In a ray collection phase, each processor element, in parallel with the other processor elements, determines which segments of the rays interpolate voxels of its associated block of data. In a segment value combination phase, each processor element, in parallel with the other processor elements, determines the integrated contribution of the interpolated voxels on the path of the ray segments traversing its block of data.

Abstract: The present invention relates to a method and apparatus that minimizes shock/vibrational motion in interposer sockets. The ability to control shock/vibration can ensure successful operation and substantially increase socket lifetime. The present invention discloses a device for maintaining a heat sink in a desired relationship to a mounting base while limiting the transmission of shock and vibrational motion to and from the heat sink includes a fastener extending from the mounting base, a spring compressed between the fastener and the heat sink, and a damper compressed between the fastener and the sink wherein the fastener maintains the spring and the damper in a compressed state such that the spring and the damper bear on said heat sink.

Abstract: A networking modem capable of full duplex communication over a telephone line is adapted for use as a component of a computer system. The modem comprises a digital signal processor (DSP) capable of implementing a plurality of digital modulation and demodulation techniques, including pulse position modulation (PPM), quadrature phase shift keying (QPSK), and quadrature amplitude modulation (QAM). The DSP implements a digital phase locked loop (DPLL), including a carrier NCO and a carrier detector to synchronize local demodulation timing to an incoming carrier signal. Available processing options include spectral agility for optimizing channel capacity, symbol shaping to compensate for evolving channel conditions, and echo cancellation.

Abstract: A method and apparatus introduces the creation and use of two record addressing functions. One function “computeRID” assigns identifiers to records, and the other function “lookupRID” performs the related task of locating a record given its identifier.

Abstract: A technique for classifying objects within an image is disclosed. In one embodiment, the technique is realized by identifying a portion of an image, and then filtering the portion of the image based upon an object characteristic and a reference within the image. The image can be a representation of a plurality of pixels, wherein at least some of the plurality of pixels are enabled to represent the identified portion of the image. The reference can be one of a reference plane or a terrain within the image.

Abstract: The real-time test controller maintains a failure database containing a history of past failures for devices under test and selectively sorts the history for the device to be tested. The diagnostic testing sequence is then rearranged with tests having higher failure rates being conducted first. If faults are detected, a message is provided to the operator and the failure database is either manually or automatically updated with the latest fault information. In this manner, a continuously updated history of faults is maintained and the most efficient testing sequence is followed, resulting in significant time and cost savings.

Abstract: A densely packaged processor-based device, such as a server. The server includes a server chassis divided into two different cooling zones, a first pressure zone and a second pressure zone. A high output fan directs air across tightly packaged, heat producing components disposed in the higher pressure zone. The higher pressure permits sufficient airflow to adequately cool the components. This zone is separated from the second zone by a baffle to prevent the high pressure air from interfering with the cooling of components in the lower pressure zone.

Abstract: Computer based apparatus and method automates gene prediction in a subject genomic sequence. A plurality of expert systems provide preliminary or intermediate gene predictions. A Bayesian network combiner combines the intermediate gene predictions and forms a final gene prediction. The final gene prediction accounts for dependencies between individual expert systems and dependencies between adjacent parts of the subject genomic sequence.

Abstract: A method is provided for scheduling execution of a plurality of threads executed in a multithreaded processor. Resource utilizations of each of the plurality of threads are measured while the plurality of threads are concurrently executing in the multithreaded processor. Each of the plurality of threads is scheduled according to the measured resource utilizations using a thread scheduler.

Abstract: An image is displayed using anamorphic video. A first portion of an image is displayed on a display at a first scale. At least one second portion of the image is displayed on the display. The at least one second portion is adjacent the first portion of the image. The second portion is displayed at a second scale higher than the first scale.

Abstract: In accordance with the present invention a method is provided for managing TCP port numbers used by applications running on a cluster. Using that method, ranges of TCP port numbers are locked (reserved) by a processor node of a cluster. An application running on one of those processor nodes uses a locked TCP port number when issuing a data packet that includes the cluster alias address as the source address. With such an invention, applications running on each processor node within a cluster will use unique TCP port numbers when using the cluster alias address. Therefore, connections between a source and destination application can be uniquely registered at the destination processor node using an index formed by a combination of the source address and the TCP port number with the destination address and TCP port number.

Abstract: The system and method of the present invention facilitates encrypting and decrypting files using a fast hardware implementation of the RC4 method to enable secure access to information resources in a computer network. The network system includes a sender computer coupled via a computer network to a receiver computer. The RC4 algorithm as implemented in hardware and its associated multiport memory (included within both the sender computer and the receiver computer) enables a fast hardware implementation of the respective encryption circuit and decryption circuit. Multi-port memory allows for at either computer site a fast hardware implementation of the RC4 encryption/decryption method where reads and writes are synchronously performed.

Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.

Abstract: A heat sink assembly for use with edge connectors, e.g., card edge connectors, of cards or printed circuit boards. The heat sink assembly provides a relatively large heat transfer capacity to control temperatures in contacts of the edge connectors which increases the current rating of the connector by allowing more current to pass through the connector. The heat sink assembly includes fins attached to the edge connector power and ground leads by direct thermal connection, such as soldering, to traces in the board. The fins are connected to the power and ground leads in an alternating or interweaved fashion. The fins are fabricated from thermal conducting material and heat is conducted to the fins where it is removed by the relatively large surface area of the fins. Adjacent fins are electrically isolated such that power and ground fins do not contact.

Abstract: A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each running a distinct copy, or instance, of an operating system. Each of the partitions has access to its own physical resources plus resources designated as shared. The partitioning is performed by assigning all resources with a configuration tree. None, some, or all, resources may be designated as shared among multiple partitions. Each individual operating instance will generally be assigned the resources it needs to execute independently and these resources will be designated as “private.” Other resources, particularly memory, can be assigned to more than one instance and shared.

Abstract: A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared.

Abstract: A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used.