Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.

Abstract: The present invention relates to a method of in-band communication, outside the standard SCSI communication protocol, between SCSI bus repeaters and initiator devices. The present invention implements the communication mode during the message phase of the SCSI protocol and allows initiators on a SCSI bus to determine the number, location and status of SCSI repeaters accessible on the SCSI bus.

Abstract: A secure system and method is provided for remotely waking a computer from a power down state. In one embodiment, a network interface card receives incoming data packets via a network connector. A control module is coupled to the network connector and is configured to search the incoming packets for a wake-up pattern. The control module also verifies that the packet's destination address matches the destination address of the network interface card. If the destination addresses match and a wake-up pattern is found, the control module decrypts an encrypted value from the incoming packet and compares the result to an expected value. A successful comparison causes the control module to assert a signal to wake up the host computer. Preferably, a standard public/private key pair encryption scheme is used, and the source of the data packet encrypts the expected value with a private key.

Abstract: Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

Abstract: A network management application provides notification of events on network devices using prepopulated notification rules. The notification rule is prepopulated by the network management application using conditions that represent the present state of the device being monitored. An associated notification action is executed when an event on a network device satisfies the conditions of the prepopulated notification rule. The notification action can be tested without actually creating a set of conditions for a device that satisfies the conditions of the notification rule.

Abstract: Single to differential interfacing. The present invention provides for an efficient solution to transform an output from a single ended source to a pair of differential signals that are provided to a differential receiver. The differential receiver is any number of devices including a differential clock receiver. The differential signals may be referenced to voltages used to receiver power supply voltages. The present invention obviates the need for an additional differential driver and its required additional devices that are need to perform transformation of a single ended signal to a pair of differential signals. There can be significant cost savings in using the single to differential interfacing that is performed in accordance with the present invention.

Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requester and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.

Abstract: A method and apparatus for logging errors in a storage device. As commands are executed by the storage device a list of previously executed commands is maintained. When an error is detected by the storage device, the previously executed commands and certain error condition codes are stored in an error log in a non-volatile memory of the storage device. The storage device is responsive to a command for reading back the values contained in the error log for diagnostic purposes.

Abstract: According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

Abstract: The present invention computer method and apparatus determines music similarity by generating a K-means (instead of Gaussian) cluster signature and a beat signature for each piece of music. The beat of the music is included in the subsequent distance measurement.

Abstract: A high voltage electrical connection between a base unit and a panel display in a portable computer wherein the base unit and the panel display are pivotably secured to each other about a hinge axis, includes a flexible high voltage electrical conductor extending from the base unit to the panel display. A portion of the electrical conductor extends along the hinge axis such that pivoting of the panel display relative to the base unit causes said portion of the flexible conductor to twist about the hinge axis rather than actively bend.

Abstract: The disclosed method and apparatus controls the rate of playback of audio data corresponding to a stream of speech. Using speech recognition, the rate of speech of the audio data is determined. The determined rate of speech is compared to a target rate. Based on the comparison, the playback rate is adjusted, i.e. increased or decreased, to match the target rate.

Abstract: An active self discovery system and method for a network. The network includes a management server having a corresponding server address and one or more managed devices. The management server includes a management database that is used to store management information and corresponding network addresses for each of the managed devices. Each managed device includes an active discovery agent that initiates management by sending its management information and network address to the management server. The managed device sends its management information upon initialization or anytime after the device becomes active on the network. Also, the managed device sends updated management information to the management server if and when the management information changes. Such changes include any status or configuration changes of the managed device or a new network address if the device's address is dynamically changed.

Abstract: A method and system for compressing video data in a computer has video processing that is distributed between preprocessing hardware in a video capture/controller card and a central processing unit of the computer. Frames of video data are passed to a motion estimation unit of the preprocessing hardware. This unit generates motion information describing inter-frame changes in the video data. Next, motion-compensated temporal filtering is performed on the frames of video data using the motion information. A video frame processing unit of the controller card, used for processing video data to the monitor, is reused for the temporal filtering of the input video data. Finally, the temporally-filtered video data is passed to the central processing unit, which performs inter-frame and/or intra-frame compression with reference to the motion information.

Abstract: A system for seamless distributed job control between a multifunction peripheral and a host. A host, such as a personal computer, is linked with one or more multifunction peripherals. Each multifunction peripheral has at least scanning and printing capability. However, the peripherals do not require extensive memory or processing capability, because the processing and storage of data is accomplished by the host. A user potentially may operate the peripheral through a peripheral interface or through a user interface of the host.

Abstract: An architecture, system and method are provided for efficiently transferring data across multiple processor buses. Cache coherency is maintained among cache storage locations within one or more of those processors, even in instances where a hit-to-modified condition occurs to those cache storage locations. A guaranteed access is maintained to bus agents operating on a first processor bus so that out-of-order or split transactions are prevented on that bus even under conditions of a hit-to-modified condition. One or more of the other processor buses undergo a defer transaction, yielding an out-of-order condition which is resolved after the initial transaction and a snoop request cycle has been placed upon the first processor bus. The present architecture, system and method thereby prevents live-lock conditions, and does so without automatically deferring each transaction yielding a hit-to-modified signal.

Abstract: A generic mounting structure is provided between a hard disk drive (HDD) and a computer. The structure includes a plurality of nubs disposed on a brace that can be fitted onto a HDD. The nubs are preferably cylindrical members having an enlarged diameter head. The computer includes, either internally or externally, a bay having a boot interface that closely receives the nubs. The boot interface includes a tapered slotted recess that closely receives the enlarged diameter head of the nubs. In a preferred embodiment, at least two different computer platforms incorporate a substantially identical bay design. Likewise, a brace having nubs oriented in a manner complementary to the bay design is fitted onto at least two different HDDs. Because the HDDs and computer platforms have common mechanical connection by virtue of the brace and bay designs, the HDDs may be exchanged between these computer platforms. In a different embodiment of the present invention, the nubs may be formed directly onto the HDD itself.

Abstract: A method of providing conversion from YUV signals to RGB signals includes the steps of determining a correspondence value between each of the Y, U, and V pixel values and the corresponding one of the R, G, and B pixel values. Three tables are generated; a Y table, a U table and a V table. During operation, each table may then be easily accessed by indexing the table with the respective Y, U or V input, to provide R,G,B data. The method may be used in a 64 bit embodiment using two registers or one register. Alternatively, the method may be used in a 32 bit embodiment. The conversion method can easily be augmented to provide color adjustment during conversion without any added complexity.

Abstract: A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

Abstract: A peripheral control interface provides access to a system area network for a plurality of peripheral devices connected to the PCI through an I/O bus. A plurality of virtual data channels is defined in local memory to which outstanding requests from peripherals are assigned. Physical channel engines implement the order requests through the assigned virtual data channel with accessed data stored in local memory. A subsequent request by a peripheral can then be immediately fulfilled from data stored in memory. Data channel context stored in memory includes the number of outstanding requests by a user to whom the channel is dedicated, and a physical channel engine can pre-fetch data in response to a plurality of outstanding requests from a peripheral thereby eliminating latency in fulfilling requests.