Abstract: Incorporation of a collateral process as a participant in a transaction is made possible by a method and system in accordance with the present invention. Typically, after the transaction is initiated, the collateral process is called and then is registered as a participant,in the transaction. A prepare signal is sent to each registered collateral process when end stage of the transaction is reached. Then, a ready signal is received from the collateral process if the collateral process is completed successfully; and an abort signal is received from the collateral process if the collateral process does not complete successfully or a violation is detected. If a ready signal is received, a commit record is written to a log, and a commit signal is sent to each registered collateral process. In response to the commit signal, a forgotten signal is received from each registered collateral process.

Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.

Abstract: A protocol for a transaction involving two homogeneous or two heterogeneous computing systems involves starting a transaction on one of the two systems, sending a request for participation in the transaction to an application resident on the other of the two systems, together with an identification and address of the transaction. Upon receipt of the request, the application will initiate a subordinate transaction through a resident (subordinate) transaction manager. The subordinate transaction manager will notify the Beginner transaction manager and at the same time cause the application to start work on the request. Later, the subordinate transaction, through the subordinate transaction manager participates in a two-phase commit protocol that concludes the transaction to ensure that all changes effected by the transaction are done, or none are done, i.e., the transaction is aborted.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A programmable operational system for managing devices participating in a network including a collection of notices, operation logic that filters the collection of notices based on at least one criteria and that generates at least one operation indicative of a state change of the network, and an automation engine that uses the at least one operation to perform at least one process in response one or more operations. The collection of notices, generated by a plurality of routines, are indicative of the state of hardware, software, and user actions that comprise the network including the state or status of one or more of the devices participating in the network. The operation logic may include an operation engine and one or more operational groups. Each operational group may further include one or more operations, each including a filter and configuration information. The operation logic may further generate at least one job and store the job into memory, where each job references an operation.

Abstract: A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Abstract: A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Abstract: A device for seamlessly providing 10BASE-T compatible data communications over an ordinary single twisted pair home phone line between multiple computers, between computers and peripherals, and between multiple peripherals. Each component that is to communicate over the home phone line will have a 10BASE-T compatible network interface card (NIC) for interfacing with the device. A transmit/receive switch is used to switch the device between a transmit mode and a receive mode. When signal are being transmitted from a component a Manchester coder decodes signals received from the NIC. A differential converter is used to convert the differential signal received from the NIC to a single signal. A modulator is used to modulate the signal to a RF signal using a modulation scheme such as PSK, QPSK, QAM or MCM schemes. A filter is used to limit the bandwidth of the modulated signal and a driver is used to amplify the signal to match the impedance of the phone line.

Abstract: An electronic commerce system includes a broker computer system having a database of scrip representing a form of currency, a vendor computer system having a database containing products which may be exchanged for the scrip, a consumer computer system with which a user may initiate transactions with the scrip, and an agent computer system to which the consumer can delegate rights to perform actions with the scrip. To delegate actions on scrip, the delegator provides the delegatee with a delegation having a list of the delegated actions. In addition, the delegator determines a delegation scrip secret (DSS) and a delegation pass phrase (DPP) and securely passes these to the delegatee. The delegatee uses the DSS to authenticate itself to servers accepting the scrip and uses the DPP to encrypt the DSS while the scrip is stored by the delegatee. To perform an action with delegated scrip, the delegatee sends a request for the action to a server.

Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.

Abstract: Iterative information retrieval from a large database of textual or text-containing documents is facilitated by automatic construction of faceted representations. Facets are chosen heuristically based on lexical dispersion, a measure of the number of different words with which a particular search expression co-occurs within a given type of lexical construct (e.g., a noun phrase) appearing in the document set. Words having high dispersion rates represent “facets” that may be used to organize the documents conceptually in accordance with the search expression, effectively providing a concise, structured summary of the contents of a result set as well as presenting a set of candidate terms for query reformulation.

Abstract: A technique for identifying multiple circuit components. More specifically, a technique for identifying the location of electrical components, such as memory cartridges which have been disposed on a substrate, is described.

Abstract: A solid state safety relay comprises: a first driver circuit; a second driver circuit; a charge disconnect transistor coupled to the first driver circuit and configured to control the flow of current along a current path; a first discharge disconnect transistor coupled to the first driver circuit and configured to control the flow of current along the current path; and a second discharge disconnect transistor coupled to the second driver circuit and configured to control the flow of current along the current path. A method of isolating an energy source from a circuit current path, comprises: turning off a first discharge disconnect transistor coupled to the circuit current path; and turning off a second discharge disconnect transistor coupled to the circuit current path to permit isolation of the energy source from the circuit current path if either one of the first discharge disconnect transistor or the second discharge disconnect transistor fails.

Abstract: A system for execution of code during power-on-self test (POST), the system including a mass storage device for storing computer programs; a microprocessor connected to the mass storage device, the microprocessor including an execution unit; a general purpose register connected to the execution unit, the general purpose register for storing a first data element; an MMX unit including a plurality of MMX registers, the MMX unit connected to the general purpose register, wherein the plurality of MMX registers are configurable as a virtual stack; a storage device connected to the microprocessor, the storage device for storing BIOS instructions; and a plurality of BIOS instructions stored on the storage device, the plurality of BIOS instructions readable by the microprocessor to thereby cause the microprocessor to execute a virtual stack push instruction wherein the first data element is moved from the general purpose register to a first of the plurality of MMX registers; and execute a virtual stack pop instructio

Abstract: An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K, wherein K is the smallest integer such that the difference between any two adjacent bytes is expressible in K bits or less, outputs an indication of K and outputs a K bit difference between the byte and an immediately prior byte, for each byte in the set.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.